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Jonathan Tremesaygues 2 years ago
commit
5e33de6e41
  1. 8
      adder2/rtl/adder2.v
  2. 13
      adder2/tb/test_adder2.py
  3. 10
      adder2_reg/rtl/adder2_reg.v
  4. 17
      adder2_reg/tb/test_adder2_reg.py
  5. 13
      adder2_reg_arst/rtl/adder2_reg_arst.v
  6. 22
      adder2_reg_arst/tb/test_adder2_reg_arst.py
  7. 8
      adder3/rtl/adder3.v
  8. 13
      adder3/tb/test_adder3.py
  9. 10
      adder3_reg/rtl/adder3_reg.v
  10. 17
      adder3_reg/tb/test_adder3_reg.py
  11. 13
      adder3_reg_arst/rtl/adder3_reg_arst.v
  12. 22
      adder3_reg_arst/tb/test_adder3_reg_arst.py
  13. 8
      adder4/rtl/adder4.v
  14. 13
      adder4/tb/test_adder4.py
  15. 10
      adder4_reg/rtl/adder4_reg.v
  16. 17
      adder4_reg/tb/test_adder4_reg.py
  17. 13
      adder4_reg_arst/rtl/adder4_reg_arst.v
  18. 22
      adder4_reg_arst/tb/test_adder4_reg_arst.py
  19. 8
      adder5/rtl/adder5.v
  20. 13
      adder5/tb/test_adder5.py
  21. 10
      adder5_reg/rtl/adder5_reg.v
  22. 17
      adder5_reg/tb/test_adder5_reg.py
  23. 13
      adder5_reg_arst/rtl/adder5_reg_arst.v
  24. 22
      adder5_reg_arst/tb/test_adder5_reg_arst.py
  25. 8
      adder6/rtl/adder6.v
  26. 13
      adder6/tb/test_adder6.py
  27. 10
      adder6_reg/rtl/adder6_reg.v
  28. 17
      adder6_reg/tb/test_adder6_reg.py
  29. 13
      adder6_reg_arst/rtl/adder6_reg_arst.v
  30. 22
      adder6_reg_arst/tb/test_adder6_reg_arst.py
  31. 8
      adder7/rtl/adder7.v
  32. 13
      adder7/tb/test_adder7.py
  33. 10
      adder7_reg/rtl/adder7_reg.v
  34. 17
      adder7_reg/tb/test_adder7_reg.py
  35. 13
      adder7_reg_arst/rtl/adder7_reg_arst.v
  36. 22
      adder7_reg_arst/tb/test_adder7_reg_arst.py
  37. 8
      adder8/rtl/adder8.v
  38. 13
      adder8/tb/test_adder8.py
  39. 10
      adder8_reg/rtl/adder8_reg.v
  40. 17
      adder8_reg/tb/test_adder8_reg.py
  41. 13
      adder8_reg_arst/rtl/adder8_reg_arst.v
  42. 22
      adder8_reg_arst/tb/test_adder8_reg_arst.py
  43. 8
      and2/rtl/and2.v
  44. 13
      and2/tb/test_and2.py
  45. 10
      and2_reg/rtl/and2_reg.v
  46. 17
      and2_reg/tb/test_and2_reg.py
  47. 13
      and2_reg_arst/rtl/and2_reg_arst.v
  48. 22
      and2_reg_arst/tb/test_and2_reg_arst.py
  49. 8
      and3/rtl/and3.v
  50. 14
      and3/tb/test_and3.py
  51. 10
      and3_reg/rtl/and3_reg.v
  52. 18
      and3_reg/tb/test_and3_reg.py
  53. 13
      and3_reg_arst/rtl/and3_reg_arst.v
  54. 23
      and3_reg_arst/tb/test_and3_reg_arst.py
  55. 8
      and4/rtl/and4.v
  56. 15
      and4/tb/test_and4.py
  57. 10
      and4_reg/rtl/and4_reg.v
  58. 19
      and4_reg/tb/test_and4_reg.py
  59. 13
      and4_reg_arst/rtl/and4_reg_arst.v
  60. 24
      and4_reg_arst/tb/test_and4_reg_arst.py
  61. 8
      and5/rtl/and5.v
  62. 16
      and5/tb/test_and5.py
  63. 10
      and5_reg/rtl/and5_reg.v
  64. 20
      and5_reg/tb/test_and5_reg.py
  65. 13
      and5_reg_arst/rtl/and5_reg_arst.v
  66. 25
      and5_reg_arst/tb/test_and5_reg_arst.py
  67. 8
      and6/rtl/and6.v
  68. 17
      and6/tb/test_and6.py
  69. 10
      and6_reg/rtl/and6_reg.v
  70. 21
      and6_reg/tb/test_and6_reg.py
  71. 13
      and6_reg_arst/rtl/and6_reg_arst.v
  72. 26
      and6_reg_arst/tb/test_and6_reg_arst.py
  73. 8
      and7/rtl/and7.v
  74. 18
      and7/tb/test_and7.py
  75. 10
      and7_reg/rtl/and7_reg.v
  76. 22
      and7_reg/tb/test_and7_reg.py
  77. 13
      and7_reg_arst/rtl/and7_reg_arst.v
  78. 27
      and7_reg_arst/tb/test_and7_reg_arst.py
  79. 8
      and8/rtl/and8.v
  80. 19
      and8/tb/test_and8.py
  81. 10
      and8_reg/rtl/and8_reg.v
  82. 23
      and8_reg/tb/test_and8_reg.py
  83. 13
      and8_reg_arst/rtl/and8_reg_arst.v
  84. 28
      and8_reg_arst/tb/test_and8_reg_arst.py
  85. 8
      or2/rtl/or2.v
  86. 13
      or2/tb/test_or2.py
  87. 10
      or2_reg/rtl/or2_reg.v
  88. 17
      or2_reg/tb/test_or2_reg.py
  89. 13
      or2_reg_arst/rtl/or2_reg_arst.v
  90. 22
      or2_reg_arst/tb/test_or2_reg_arst.py
  91. 8
      or3/rtl/or3.v
  92. 14
      or3/tb/test_or3.py
  93. 10
      or3_reg/rtl/or3_reg.v
  94. 18
      or3_reg/tb/test_or3_reg.py
  95. 13
      or3_reg_arst/rtl/or3_reg_arst.v
  96. 23
      or3_reg_arst/tb/test_or3_reg_arst.py
  97. 8
      or4/rtl/or4.v
  98. 15
      or4/tb/test_or4.py
  99. 10
      or4_reg/rtl/or4_reg.v
  100. 19
      or4_reg/tb/test_or4_reg.py

8
adder2/rtl/adder2.v

@ -0,0 +1,8 @@
`timescale 1ns / 1ps
module adder2(z, b, a);
output [2:0] z;
input [1:0] a, b;
assign z = a + b;
endmodule

13
adder2/tb/test_adder2.py

@ -0,0 +1,13 @@
import itertools
import cocotb
from cocotb.triggers import Timer
@cocotb.test()
def test_adder2(dut):
for b, a in itertools.product(range(2 ** 2), repeat=2):
dut.a = a
dut.b = b
yield Timer(1, units='ns')
z = a + b
assert z == dut.z

10
adder2_reg/rtl/adder2_reg.v

@ -0,0 +1,10 @@
`timescale 1ns / 1ps
module adder2_reg(z, b, a, clk);
output reg [2:0] z;
input [1:0] a, b;
input clk;
always @(posedge clk)
z <= a + b;
endmodule

17
adder2_reg/tb/test_adder2_reg.py

@ -0,0 +1,17 @@
import itertools
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import Timer
@cocotb.test()
def test_adder2_reg(dut):
cocotb.fork(Clock(dut.clk, 10, units='ns').start())
yield Timer(5, units='ns')
for b, a in itertools.product(range(2 ** 2), repeat=2):
dut.a = a
dut.b = b
yield Timer(10, units='ns')
z = a + b
assert z == dut.z

13
adder2_reg_arst/rtl/adder2_reg_arst.v

@ -0,0 +1,13 @@
`timescale 1ns / 1ps
module adder2_reg_arst(z, b, a, clk, rst);
output reg [2:0] z;
input [1:0] a, b;
input clk, rst;
always @(posedge clk, posedge rst)
if (rst)
z <= 0;
else
z <= a + b;
endmodule

22
adder2_reg_arst/tb/test_adder2_reg_arst.py

@ -0,0 +1,22 @@
import itertools
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import Timer
@cocotb.test()
def test_adder2_reg_arst(dut):
cocotb.fork(Clock(dut.clk, 10, units='ns').start())
yield Timer(5, units='ns')
dut.rst = True
yield Timer(10, units='ns')
dut.rst = False
assert dut.z == False
for b, a in itertools.product(range(2 ** 2), repeat=2):
dut.a = a
dut.b = b
yield Timer(10, units='ns')
z = a + b
assert z == dut.z

8
adder3/rtl/adder3.v

@ -0,0 +1,8 @@
`timescale 1ns / 1ps
module adder3(z, b, a);
output [3:0] z;
input [2:0] a, b;
assign z = a + b;
endmodule

13
adder3/tb/test_adder3.py

@ -0,0 +1,13 @@
import itertools
import cocotb
from cocotb.triggers import Timer
@cocotb.test()
def test_adder3(dut):
for b, a in itertools.product(range(2 ** 3), repeat=2):
dut.a = a
dut.b = b
yield Timer(1, units='ns')
z = a + b
assert z == dut.z

10
adder3_reg/rtl/adder3_reg.v

@ -0,0 +1,10 @@
`timescale 1ns / 1ps
module adder3_reg(z, b, a, clk);
output reg [3:0] z;
input [2:0] a, b;
input clk;
always @(posedge clk)
z <= a + b;
endmodule

17
adder3_reg/tb/test_adder3_reg.py

@ -0,0 +1,17 @@
import itertools
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import Timer
@cocotb.test()
def test_adder3_reg(dut):
cocotb.fork(Clock(dut.clk, 10, units='ns').start())
yield Timer(5, units='ns')
for b, a in itertools.product(range(2 ** 3), repeat=2):
dut.a = a
dut.b = b
yield Timer(10, units='ns')
z = a + b
assert z == dut.z

13
adder3_reg_arst/rtl/adder3_reg_arst.v

@ -0,0 +1,13 @@
`timescale 1ns / 1ps
module adder3_reg_arst(z, b, a, clk, rst);
output reg [3:0] z;
input [2:0] a, b;
input clk, rst;
always @(posedge clk, posedge rst)
if (rst)
z <= 0;
else
z <= a + b;
endmodule

22
adder3_reg_arst/tb/test_adder3_reg_arst.py

@ -0,0 +1,22 @@
import itertools
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import Timer
@cocotb.test()
def test_adder3_reg_arst(dut):
cocotb.fork(Clock(dut.clk, 10, units='ns').start())
yield Timer(5, units='ns')
dut.rst = True
yield Timer(10, units='ns')
dut.rst = False
assert dut.z == False
for b, a in itertools.product(range(2 ** 3), repeat=2):
dut.a = a
dut.b = b
yield Timer(10, units='ns')
z = a + b
assert z == dut.z

8
adder4/rtl/adder4.v

@ -0,0 +1,8 @@
`timescale 1ns / 1ps
module adder4(z, b, a);
output [4:0] z;
input [3:0] a, b;
assign z = a + b;
endmodule

13
adder4/tb/test_adder4.py

@ -0,0 +1,13 @@
import itertools
import cocotb
from cocotb.triggers import Timer
@cocotb.test()
def test_adder4(dut):
for b, a in itertools.product(range(2 ** 4), repeat=2):
dut.a = a
dut.b = b
yield Timer(1, units='ns')
z = a + b
assert z == dut.z

10
adder4_reg/rtl/adder4_reg.v

@ -0,0 +1,10 @@
`timescale 1ns / 1ps
module adder4_reg(z, b, a, clk);
output reg [4:0] z;
input [3:0] a, b;
input clk;
always @(posedge clk)
z <= a + b;
endmodule

17
adder4_reg/tb/test_adder4_reg.py

@ -0,0 +1,17 @@
import itertools
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import Timer
@cocotb.test()
def test_adder4_reg(dut):
cocotb.fork(Clock(dut.clk, 10, units='ns').start())
yield Timer(5, units='ns')
for b, a in itertools.product(range(2 ** 4), repeat=2):
dut.a = a
dut.b = b
yield Timer(10, units='ns')
z = a + b
assert z == dut.z

13
adder4_reg_arst/rtl/adder4_reg_arst.v

@ -0,0 +1,13 @@
`timescale 1ns / 1ps
module adder4_reg_arst(z, b, a, clk, rst);
output reg [4:0] z;
input [3:0] a, b;
input clk, rst;
always @(posedge clk, posedge rst)
if (rst)
z <= 0;
else
z <= a + b;
endmodule

22
adder4_reg_arst/tb/test_adder4_reg_arst.py

@ -0,0 +1,22 @@
import itertools
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import Timer
@cocotb.test()
def test_adder4_reg_arst(dut):
cocotb.fork(Clock(dut.clk, 10, units='ns').start())
yield Timer(5, units='ns')
dut.rst = True
yield Timer(10, units='ns')
dut.rst = False
assert dut.z == False
for b, a in itertools.product(range(2 ** 4), repeat=2):
dut.a = a
dut.b = b
yield Timer(10, units='ns')
z = a + b
assert z == dut.z

8
adder5/rtl/adder5.v

@ -0,0 +1,8 @@
`timescale 1ns / 1ps
module adder5(z, b, a);
output [5:0] z;
input [4:0] a, b;
assign z = a + b;
endmodule

13
adder5/tb/test_adder5.py

@ -0,0 +1,13 @@
import itertools
import cocotb
from cocotb.triggers import Timer
@cocotb.test()
def test_adder5(dut):
for b, a in itertools.product(range(2 ** 5), repeat=2):
dut.a = a
dut.b = b
yield Timer(1, units='ns')
z = a + b
assert z == dut.z

10
adder5_reg/rtl/adder5_reg.v

@ -0,0 +1,10 @@
`timescale 1ns / 1ps
module adder5_reg(z, b, a, clk);
output reg [5:0] z;
input [4:0] a, b;
input clk;
always @(posedge clk)
z <= a + b;
endmodule

17
adder5_reg/tb/test_adder5_reg.py

@ -0,0 +1,17 @@
import itertools
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import Timer
@cocotb.test()
def test_adder5_reg(dut):
cocotb.fork(Clock(dut.clk, 10, units='ns').start())
yield Timer(5, units='ns')
for b, a in itertools.product(range(2 ** 5), repeat=2):
dut.a = a
dut.b = b
yield Timer(10, units='ns')
z = a + b
assert z == dut.z

13
adder5_reg_arst/rtl/adder5_reg_arst.v

@ -0,0 +1,13 @@
`timescale 1ns / 1ps
module adder5_reg_arst(z, b, a, clk, rst);
output reg [5:0] z;
input [4:0] a, b;
input clk, rst;
always @(posedge clk, posedge rst)
if (rst)
z <= 0;
else
z <= a + b;
endmodule

22
adder5_reg_arst/tb/test_adder5_reg_arst.py

@ -0,0 +1,22 @@
import itertools
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import Timer
@cocotb.test()
def test_adder5_reg_arst(dut):
cocotb.fork(Clock(dut.clk, 10, units='ns').start())
yield Timer(5, units='ns')
dut.rst = True
yield Timer(10, units='ns')
dut.rst = False
assert dut.z == False
for b, a in itertools.product(range(2 ** 5), repeat=2):
dut.a = a
dut.b = b
yield Timer(10, units='ns')
z = a + b
assert z == dut.z

8
adder6/rtl/adder6.v

@ -0,0 +1,8 @@
`timescale 1ns / 1ps
module adder6(z, b, a);
output [6:0] z;
input [5:0] a, b;
assign z = a + b;
endmodule

13
adder6/tb/test_adder6.py

@ -0,0 +1,13 @@
import itertools
import cocotb
from cocotb.triggers import Timer
@cocotb.test()
def test_adder6(dut):
for b, a in itertools.product(range(2 ** 6), repeat=2):
dut.a = a
dut.b = b
yield Timer(1, units='ns')
z = a + b
assert z == dut.z

10
adder6_reg/rtl/adder6_reg.v

@ -0,0 +1,10 @@
`timescale 1ns / 1ps
module adder6_reg(z, b, a, clk);
output reg [6:0] z;
input [5:0] a, b;
input clk;
always @(posedge clk)
z <= a + b;
endmodule

17
adder6_reg/tb/test_adder6_reg.py

@ -0,0 +1,17 @@
import itertools
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import Timer
@cocotb.test()
def test_adder6_reg(dut):
cocotb.fork(Clock(dut.clk, 10, units='ns').start())
yield Timer(5, units='ns')
for b, a in itertools.product(range(2 ** 6), repeat=2):
dut.a = a
dut.b = b
yield Timer(10, units='ns')
z = a + b
assert z == dut.z

13
adder6_reg_arst/rtl/adder6_reg_arst.v

@ -0,0 +1,13 @@
`timescale 1ns / 1ps
module adder6_reg_arst(z, b, a, clk, rst);
output reg [6:0] z;
input [5:0] a, b;
input clk, rst;
always @(posedge clk, posedge rst)
if (rst)
z <= 0;
else
z <= a + b;
endmodule

22
adder6_reg_arst/tb/test_adder6_reg_arst.py

@ -0,0 +1,22 @@
import itertools
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import Timer
@cocotb.test()
def test_adder6_reg_arst(dut):
cocotb.fork(Clock(dut.clk, 10, units='ns').start())
yield Timer(5, units='ns')
dut.rst = True
yield Timer(10, units='ns')
dut.rst = False
assert dut.z == False
for b, a in itertools.product(range(2 ** 6), repeat=2):
dut.a = a
dut.b = b
yield Timer(10, units='ns')
z = a + b
assert z == dut.z

8
adder7/rtl/adder7.v

@ -0,0 +1,8 @@
`timescale 1ns / 1ps
module adder7(z, b, a);
output [7:0] z;
input [6:0] a, b;
assign z = a + b;
endmodule

13
adder7/tb/test_adder7.py

@ -0,0 +1,13 @@
import itertools
import cocotb
from cocotb.triggers import Timer
@cocotb.test()
def test_adder7(dut):
for b, a in itertools.product(range(2 ** 7), repeat=2):
dut.a = a
dut.b = b
yield Timer(1, units='ns')
z = a + b
assert z == dut.z

10
adder7_reg/rtl/adder7_reg.v

@ -0,0 +1,10 @@
`timescale 1ns / 1ps
module adder7_reg(z, b, a, clk);
output reg [7:0] z;
input [6:0] a, b;
input clk;
always @(posedge clk)
z <= a + b;
endmodule

17
adder7_reg/tb/test_adder7_reg.py

@ -0,0 +1,17 @@
import itertools
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import Timer
@cocotb.test()
def test_adder7_reg(dut):
cocotb.fork(Clock(dut.clk, 10, units='ns').start())
yield Timer(5, units='ns')
for b, a in itertools.product(range(2 ** 7), repeat=2):
dut.a = a
dut.b = b
yield Timer(10, units='ns')
z = a + b
assert z == dut.z

13
adder7_reg_arst/rtl/adder7_reg_arst.v

@ -0,0 +1,13 @@
`timescale 1ns / 1ps
module adder7_reg_arst(z, b, a, clk, rst);
output reg [7:0] z;
input [6:0] a, b;
input clk, rst;
always @(posedge clk, posedge rst)
if (rst)
z <= 0;
else
z <= a + b;
endmodule

22
adder7_reg_arst/tb/test_adder7_reg_arst.py

@ -0,0 +1,22 @@
import itertools
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import Timer
@cocotb.test()
def test_adder7_reg_arst(dut):
cocotb.fork(Clock(dut.clk, 10, units='ns').start())
yield Timer(5, units='ns')
dut.rst = True
yield Timer(10, units='ns')
dut.rst = False
assert dut.z == False
for b, a in itertools.product(range(2 ** 7), repeat=2):
dut.a = a
dut.b = b
yield Timer(10, units='ns')
z = a + b
assert z == dut.z

8
adder8/rtl/adder8.v

@ -0,0 +1,8 @@
`timescale 1ns / 1ps
module adder8(z, b, a);
output [8:0] z;
input [7:0] a, b;
assign z = a + b;
endmodule

13
adder8/tb/test_adder8.py

@ -0,0 +1,13 @@
import itertools
import cocotb
from cocotb.triggers import Timer
@cocotb.test()
def test_adder8(dut):
for b, a in itertools.product(range(2 ** 8), repeat=2):
dut.a = a
dut.b = b
yield Timer(1, units='ns')
z = a + b
assert z == dut.z

10
adder8_reg/rtl/adder8_reg.v

@ -0,0 +1,10 @@
`timescale 1ns / 1ps
module adder8_reg(z, b, a, clk);
output reg [8:0] z;
input [7:0] a, b;
input clk;
always @(posedge clk)
z <= a + b;
endmodule

17
adder8_reg/tb/test_adder8_reg.py

@ -0,0 +1,17 @@
import itertools
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import Timer
@cocotb.test()
def test_adder8_reg(dut):
cocotb.fork(Clock(dut.clk, 10, units='ns').start())
yield Timer(5, units='ns')
for b, a in itertools.product(range(2 ** 8), repeat=2):
dut.a = a
dut.b = b
yield Timer(10, units='ns')
z = a + b
assert z == dut.z

13
adder8_reg_arst/rtl/adder8_reg_arst.v

@ -0,0 +1,13 @@
`timescale 1ns / 1ps
module adder8_reg_arst(z, b, a, clk, rst);
output reg [8:0] z;
input [7:0] a, b;
input clk, rst;
always @(posedge clk, posedge rst)
if (rst)
z <= 0;
else
z <= a + b;
endmodule

22
adder8_reg_arst/tb/test_adder8_reg_arst.py

@ -0,0 +1,22 @@
import itertools
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import Timer
@cocotb.test()
def test_adder8_reg_arst(dut):
cocotb.fork(Clock(dut.clk, 10, units='ns').start())
yield Timer(5, units='ns')
dut.rst = True
yield Timer(10, units='ns')
dut.rst = False
assert dut.z == False
for b, a in itertools.product(range(2 ** 8), repeat=2):
dut.a = a
dut.b = b
yield Timer(10, units='ns')
z = a + b
assert z == dut.z

8
and2/rtl/and2.v

@ -0,0 +1,8 @@
`timescale 1ns / 1ps
module and2(z, a, b);
output z;
input a, b;
assign z = a & b;
endmodule

13
and2/tb/test_and2.py

@ -0,0 +1,13 @@
import itertools
import cocotb
from cocotb.triggers import Timer
@cocotb.test()
def test_and2(dut):
for b, a in itertools.product((False, True), repeat=2):
dut.a = a
dut.b = b
yield Timer(1, units='ns')
z = a & b
assert z == dut.z

10
and2_reg/rtl/and2_reg.v

@ -0,0 +1,10 @@
`timescale 1ns / 1ps
module and2_reg(z, a, b, clk);
output reg z;
input a, b;
input clk;
always @(posedge clk)
z <= a & b;
endmodule

17
and2_reg/tb/test_and2_reg.py

@ -0,0 +1,17 @@
import itertools
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import Timer
@cocotb.test()
def test_and2_reg(dut):
cocotb.fork(Clock(dut.clk, 10, units='ns').start())
yield Timer(5, units='ns')
for b, a in itertools.product((False, True), repeat=2):
dut.a = a
dut.b = b
yield Timer(10, units='ns')
z = a & b
assert z == dut.z

13
and2_reg_arst/rtl/and2_reg_arst.v

@ -0,0 +1,13 @@
`timescale 1ns / 1ps
module and2_reg_arst(z, a, b, clk, rst);
output reg z;
input a, b;
input clk, rst;
always @(posedge clk, posedge rst)
if (rst)
z <= 0;
else
z <= a & b;
endmodule

22
and2_reg_arst/tb/test_and2_reg_arst.py

@ -0,0 +1,22 @@
import itertools
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import Timer
@cocotb.test()
def test_and2_reg_arst(dut):
cocotb.fork(Clock(dut.clk, 10, units='ns').start())
yield Timer(5, units='ns')
dut.rst = True
yield Timer(10, units='ns')
dut.rst = False
assert dut.z == False
for b, a in itertools.product((False, True), repeat=2):
dut.a = a
dut.b = b
yield Timer(10, units='ns')
z = a & b
assert z == dut.z

8
and3/rtl/and3.v

@ -0,0 +1,8 @@
`timescale 1ns / 1ps
module and3(z, a, b, c);
output z;
input a, b, c;
assign z = a & b & c;
endmodule

14
and3/tb/test_and3.py

@ -0,0 +1,14 @@
import itertools
import cocotb
from cocotb.triggers import Timer
@cocotb.test()
def test_and3(dut):
for c, b, a in itertools.product((False, True), repeat=3):
dut.a = a
dut.b = b
dut.c = c
yield Timer(1, units='ns')
z = a & b & c
assert z == dut.z

10
and3_reg/rtl/and3_reg.v

@ -0,0 +1,10 @@
`timescale 1ns / 1ps
module and3_reg(z, a, b, c, clk);
output reg z;
input a, b, c;
input clk;
always @(posedge clk)
z <= a & b & c;
endmodule

18
and3_reg/tb/test_and3_reg.py

@ -0,0 +1,18 @@
import itertools
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import Timer
@cocotb.test()
def test_and3_reg(dut):
cocotb.fork(Clock(dut.clk, 10, units='ns').start())
yield Timer(5, units='ns')
for c, b, a in itertools.product((False, True), repeat=3):
dut.a = a
dut.b = b
dut.c = c
yield Timer(10, units='ns')
z = a & b & c
assert z == dut.z

13
and3_reg_arst/rtl/and3_reg_arst.v

@ -0,0 +1,13 @@
`timescale 1ns / 1ps
module and3_reg_arst(z, a, b, c, clk, rst);
output reg z;
input a, b, c;
input clk, rst;
always @(posedge clk, posedge rst)
if (rst)
z <= 0;
else
z <= a & b & c;
endmodule

23
and3_reg_arst/tb/test_and3_reg_arst.py

@ -0,0 +1,23 @@
import itertools
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import Timer
@cocotb.test()
def test_and3_reg_arst(dut):
cocotb.fork(Clock(dut.clk, 10, units='ns').start())
yield Timer(5, units='ns')
dut.rst = True
yield Timer(10, units='ns')
dut.rst = False
assert dut.z == False
for c, b, a in itertools.product((False, True), repeat=3):
dut.a = a
dut.b = b
dut.c = c
yield Timer(10, units='ns')
z = a & b & c
assert z == dut.z

8
and4/rtl/and4.v

@ -0,0 +1,8 @@
`timescale 1ns / 1ps
module and4(z, a, b, c, d);
output z;
input a, b, c, d;
assign z = a & b & c & d;
endmodule

15
and4/tb/test_and4.py

@ -0,0 +1,15 @@
import itertools
import cocotb
from cocotb.triggers import Timer
@cocotb.test()
def test_and4(dut):
for d, c, b, a in itertools.product((False, True), repeat=4):
dut.a = a
dut.b = b
dut.c = c
dut.d = d
yield Timer(1, units='ns')
z = a & b & c & d
assert z == dut.z

10
and4_reg/rtl/and4_reg.v

@ -0,0 +1,10 @@
`timescale 1ns / 1ps
module and4_reg(z, a, b, c, d, clk);
output reg z;
input a, b, c, d;
input clk;
always @(posedge clk)
z <= a & b & c & d;
endmodule

19
and4_reg/tb/test_and4_reg.py

@ -0,0 +1,19 @@
import itertools
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import Timer
@cocotb.test()
def test_and4_reg(dut):
cocotb.fork(Clock(dut.clk, 10, units='ns').start())
yield Timer(5, units='ns')
for d, c, b, a in itertools.product((False, True), repeat=4):
dut.a = a
dut.b = b
dut.c = c
dut.d = d
yield Timer(10, units='ns')
z = a & b & c & d
assert z == dut.z

13
and4_reg_arst/rtl/and4_reg_arst.v

@ -0,0 +1,13 @@
`timescale 1ns / 1ps
module and4_reg_arst(z, a, b, c, d, clk, rst);
output reg z;
input a, b, c, d;
input clk, rst;
always @(posedge clk, posedge rst)
if (rst)
z <= 0;
else
z <= a & b & c & d;
endmodule

24
and4_reg_arst/tb/test_and4_reg_arst.py

@ -0,0 +1,24 @@
import itertools
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import Timer
@cocotb.test()
def test_and4_reg_arst(dut):
cocotb.fork(Clock(dut.clk, 10, units='ns').start())
yield Timer(5, units='ns')
dut.rst = True
yield Timer(10, units='ns')
dut.rst = False
assert dut.z == False
for d, c, b, a in itertools.product((False, True), repeat=4):
dut.a = a
dut.b = b
dut.c = c
dut.d = d
yield Timer(10, units='ns')
z = a & b & c & d
assert z == dut.z

8
and5/rtl/and5.v

@ -0,0 +1,8 @@
`timescale 1ns / 1ps
module and5(z, a, b, c, d, e);
output z;
input a, b, c, d, e;
assign z = a & b & c & d & e;
endmodule

16
and5/tb/test_and5.py

@ -0,0 +1,16 @@
import itertools
import cocotb
from cocotb.triggers import Timer
@cocotb.test()
def test_and5(dut):
for e, d, c, b, a in itertools.product((False, True), repeat=5):
dut.a = a
dut.b = b
dut.c = c
dut.d = d
dut.e = e
yield Timer(1, units='ns')
z = a & b & c & d & e
assert z == dut.z

10
and5_reg/rtl/and5_reg.v

@ -0,0 +1,10 @@
`timescale 1ns / 1ps
module and5_reg(z, a, b, c, d, e, clk);
output reg z;
input a, b, c, d, e;
input clk;
always @(posedge clk)
z <= a & b & c & d & e;
endmodule

20
and5_reg/tb/test_and5_reg.py

@ -0,0 +1,20 @@
import itertools
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import Timer
@cocotb.test()
def test_and5_reg(dut):
cocotb.fork(Clock(dut.clk, 10, units='ns').start())
yield Timer(5, units='ns')
for e, d, c, b, a in itertools.product((False, True), repeat=5):
dut.a = a
dut.b = b
dut.c = c
dut.d = d
dut.e = e
yield Timer(10, units='ns')
z = a & b & c & d & e
assert z == dut.z

13
and5_reg_arst/rtl/and5_reg_arst.v

@ -0,0 +1,13 @@
`timescale 1ns / 1ps
module and5_reg_arst(z, a, b, c, d, e, clk, rst);
output reg z;
input a, b, c, d, e;
input clk, rst;
always @(posedge clk, posedge rst)
if (rst)
z <= 0;
else
z <= a & b & c & d & e;
endmodule

25
and5_reg_arst/tb/test_and5_reg_arst.py

@ -0,0 +1,25 @@
import itertools
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import Timer
@cocotb.test()
def test_and5_reg_arst(dut):
cocotb.fork(Clock(dut.clk, 10, units='ns').start())
yield Timer(5, units='ns')
dut.rst = True
yield Timer(10, units='ns')
dut.rst = False
assert dut.z == False
for e, d, c, b, a in itertools.product((False, True), repeat=5):
dut.a = a
dut.b = b
dut.c = c
dut.d = d
dut.e = e
yield Timer(10, units='ns')
z = a & b & c & d & e
assert z == dut.z

8
and6/rtl/and6.v

@ -0,0 +1,8 @@
`timescale 1ns / 1ps
module and6(z, a, b, c, d, e, f);
output z;
input a, b, c, d, e, f;
assign z = a & b & c & d & e & f;
endmodule

17
and6/tb/test_and6.py

@ -0,0 +1,17 @@
import itertools
import cocotb
from cocotb.triggers import Timer
@cocotb.test()
def test_and6(dut):
for f, e, d, c, b, a in itertools.product((False, True), repeat=6):
dut.a = a
dut.b = b
dut.c = c
dut.d = d
dut.e = e
dut.f = f
yield Timer(1, units='ns')
z = a & b & c & d & e & f
assert z == dut.z

10
and6_reg/rtl/and6_reg.v

@ -0,0 +1,10 @@
`timescale 1ns / 1ps
module and6_reg(z, a, b, c, d, e, f, clk);
output reg z;
input a, b, c, d, e, f;
input clk;
always @(posedge clk)
z <= a & b & c & d & e & f;
endmodule

21
and6_reg/tb/test_and6_reg.py

@ -0,0 +1,21 @@
import itertools
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import Timer
@cocotb.test()
def test_and6_reg(dut):
cocotb.fork(Clock(dut.clk, 10, units='ns').start())
yield Timer(5, units='ns')
for f, e, d, c, b, a in itertools.product((False, True), repeat=6):
dut.a = a
dut.b = b
dut.c = c
dut.d = d
dut.e = e
dut.f = f
yield Timer(10, units='ns')
z = a & b & c & d & e & f
assert z == dut.z

13
and6_reg_arst/rtl/and6_reg_arst.v

@ -0,0 +1,13 @@
`timescale 1ns / 1ps
module and6_reg_arst(z, a, b, c, d, e, f, clk, rst);
output reg z;
input a, b, c, d, e, f;
input clk, rst;
always @(posedge clk, posedge rst)
if (rst)
z <= 0;
else
z <= a & b & c & d & e & f;
endmodule

26
and6_reg_arst/tb/test_and6_reg_arst.py

@ -0,0 +1,26 @@
import itertools
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import Timer
@cocotb.test()
def test_and6_reg_arst(dut):
cocotb.fork(Clock(dut.clk, 10, units='ns').start())
yield Timer(5, units='ns')
dut.rst = True
yield Timer(10, units='ns')
dut.rst = False
assert dut.z == False
for f, e, d, c, b, a in itertools.product((False, True), repeat=6):
dut.a = a
dut.b = b
dut.c = c
dut.d = d
dut.e = e
dut.f = f
yield Timer(10, units='ns')
z = a & b & c & d & e & f
assert z == dut.z

8
and7/rtl/and7.v

@ -0,0 +1,8 @@
`timescale 1ns / 1ps
module and7(z, a, b, c, d, e, f, g);
output z;
input a, b, c, d, e, f, g;
assign z = a & b & c & d & e & f & g;
endmodule

18
and7/tb/test_and7.py

@ -0,0 +1,18 @@
import itertools
import cocotb
from cocotb.triggers import Timer
@cocotb.test()
def test_and7(dut):
for g, f, e, d, c, b, a in itertools.product((False, True), repeat=7):
dut.a = a
dut.b = b
dut.c = c
dut.d = d
dut.e = e
dut.f = f
dut.g = g
yield Timer(1, units='ns')
z = a & b & c & d & e & f & g
assert z == dut.z

10
and7_reg/rtl/and7_reg.v

@ -0,0 +1,10 @@
`timescale 1ns / 1ps
module and7_reg(z, a, b, c, d, e, f, g, clk);
output reg z;
input a, b, c, d, e, f, g;
input clk;
always @(posedge clk)
z <= a & b & c & d & e & f & g;
endmodule

22
and7_reg/tb/test_and7_reg.py

@ -0,0 +1,22 @@
import itertools
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import Timer
@cocotb.test()
def test_and7_reg(dut):
cocotb.fork(Clock(dut.clk, 10, units='ns').start())
yield Timer(5, units='ns')
for g, f, e, d, c, b, a in itertools.product((False, True), repeat=7):
dut.a = a
dut.b = b
dut.c = c
dut.d = d
dut.e = e
dut.f = f
dut.g = g
yield Timer(10, units='ns')
z = a & b & c & d & e & f & g
assert z == dut.z

13
and7_reg_arst/rtl/and7_reg_arst.v

@ -0,0 +1,13 @@
`timescale 1ns / 1ps
module and7_reg_arst(z, a, b, c, d, e, f, g, clk, rst);
output reg z;
input a, b, c, d, e, f, g;
input clk, rst;
always @(posedge clk, posedge rst)
if (rst)
z <= 0;
else
z <= a & b & c & d & e & f & g;
endmodule

27
and7_reg_arst/tb/test_and7_reg_arst.py

@ -0,0 +1,27 @@
import itertools
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import Timer
@cocotb.test()
def test_and7_reg_arst(dut):
cocotb.fork(Clock(dut.clk, 10, units='ns').start())
yield Timer(5, units='ns')
dut.rst = True
yield Timer(10, units='ns')
dut.rst = False
assert dut.z == False
for g, f, e, d, c, b, a in itertools.product((False, True), repeat=7):
dut.a = a
dut.b = b
dut.c = c
dut.d = d
dut.e = e
dut.f = f
dut.g = g
yield Timer(10, units='ns')
z = a & b & c & d & e & f & g
assert z == dut.z

8
and8/rtl/and8.v

@ -0,0 +1,8 @@
`timescale 1ns / 1ps
module and8(z, a, b, c, d, e, f, g, h);
output z;
input a, b, c, d, e, f, g, h;
assign z = a & b & c & d & e & f & g & h;
endmodule

19
and8/tb/test_and8.py

@ -0,0 +1,19 @@
import itertools
import cocotb
from cocotb.triggers import Timer
@cocotb.test()
def test_and8(dut):
for h, g, f, e, d, c, b, a in itertools.product((False, True), repeat=8):
dut.a = a
dut.b = b
dut.c = c
dut.d = d
dut.e = e
dut.f = f
dut.g = g
dut.h = h
yield Timer(1, units='ns')
z = a & b & c & d & e & f & g & h
assert z == dut.z

10
and8_reg/rtl/and8_reg.v

@ -0,0 +1,10 @@
`timescale 1ns / 1ps
module and8_reg(z, a, b, c, d, e, f, g, h, clk);
output reg z;
input a, b, c, d, e, f, g, h;
input clk;
always @(posedge clk)
z <= a & b & c & d & e & f & g & h;
endmodule

23
and8_reg/tb/test_and8_reg.py

@ -0,0 +1,23 @@
import itertools
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import Timer
@cocotb.test()
def test_and8_reg(dut):
cocotb.fork(Clock(dut.clk, 10, units='ns').start())
yield Timer(5, units='ns')
for h, g, f, e, d, c, b, a in itertools.product((False, True), repeat=8):
dut.a = a
dut.b = b
dut.c = c
dut.d = d
dut.e = e
dut.f = f
dut.g = g
dut.h = h
yield Timer(10, units='ns')
z = a & b & c & d & e & f & g & h
assert z == dut.z

13
and8_reg_arst/rtl/and8_reg_arst.v

@ -0,0 +1,13 @@
`timescale 1ns / 1ps
module and8_reg_arst(z, a, b, c, d, e, f, g, h, clk, rst);
output reg z;
input a, b, c, d, e, f, g, h;
input clk, rst;
always @(posedge clk, posedge rst)
if (rst)
z <= 0;
else
z <= a & b & c & d & e & f & g & h;
endmodule

28
and8_reg_arst/tb/test_and8_reg_arst.py

@ -0,0 +1,28 @@
import itertools
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import Timer
@cocotb.test()
def test_and8_reg_arst(dut):
cocotb.fork(Clock(dut.clk, 10, units='ns').start())
yield Timer(5, units='ns')
dut.rst = True
yield Timer(10, units='ns')
dut.rst = False
assert dut.z == False
for h, g, f, e, d, c, b, a in itertools.product((False, True), repeat=8):
dut.a = a
dut.b = b
dut.c = c
dut.d = d
dut.e = e
dut.f = f
dut.g = g
dut.h = h
yield Timer(10, units='ns')
z = a & b & c & d & e & f & g & h
assert z == dut.z

8
or2/rtl/or2.v

@ -0,0 +1,8 @@
`timescale 1ns / 1ps
module or2(z, a, b);
output z;
input a, b;
assign z = a | b;
endmodule

13
or2/tb/test_or2.py

@ -0,0 +1,13 @@
import itertools
import cocotb
from cocotb.triggers import Timer
@cocotb.test()
def test_or2(dut):
for b, a in itertools.product((False, True), repeat=2):
dut.a = a
dut.b = b
yield Timer(1, units='ns')
z = a | b
assert z == dut.z

10
or2_reg/rtl/or2_reg.v

@ -0,0 +1,10 @@
`timescale 1ns / 1ps
module or2_reg(z, a, b, clk);
output reg z;
input a, b;
input clk;
always @(posedge clk)
z <= a | b;
endmodule

17
or2_reg/tb/test_or2_reg.py

@ -0,0 +1,17 @@
import itertools
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import Timer
@cocotb.test()
def test_or2_reg(dut):
cocotb.fork(Clock(dut.clk, 10, units='ns').start())
yield Timer(5, units='ns')
for b, a in itertools.pro