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`timescale 1ns / 1ps
module adder6_reg_arst(z, b, a, clk, rst);
output reg [6:0] z;
input [5:0] a, b;
input clk, rst;
always @(posedge clk, posedge rst)
if (rst)
z <= 0;
else
z <= a + b;
endmodule