Browse Source

Import cores

master
commit
fb3795683d
220 changed files with 10991086 additions and 0 deletions
  1. +9
    -0
      k1g1/k1g1.kcf
  2. +58
    -0
      k1g1/rtl/ConfigurationStorage.v
  3. +69
    -0
      k1g1/rtl/IOAdapter.v
  4. +84
    -0
      k1g1/rtl/LogicElement.v
  5. +110
    -0
      k1g1/rtl/LogicTile.v
  6. +52
    -0
      k1g1/rtl/LookUpTable.v
  7. +53
    -0
      k1g1/rtl/Multiplexer.v
  8. +152
    -0
      k1g1/rtl/SwitchBox.v
  9. +169
    -0
      k1g1/rtl/k1g1.v
  10. +93
    -0
      k1g1/techlib/cells.v
  11. +9
    -0
      k1g100/k1g100.kcf
  12. +58
    -0
      k1g100/rtl/ConfigurationStorage.v
  13. +188
    -0
      k1g100/rtl/IOAdapter.v
  14. +84
    -0
      k1g100/rtl/LogicElement.v
  15. +137
    -0
      k1g100/rtl/LogicTile.v
  16. +56
    -0
      k1g100/rtl/LookUpTable.v
  17. +53
    -0
      k1g100/rtl/Multiplexer.v
  18. +950
    -0
      k1g100/rtl/SwitchBox.v
  19. +929
    -0
      k1g100/rtl/k1g100.v
  20. +97
    -0
      k1g100/techlib/cells.v
  21. +9
    -0
      k1g100k/k1g100k.kcf
  22. +58
    -0
      k1g100k/rtl/ConfigurationStorage.v
  23. +188
    -0
      k1g100k/rtl/IOAdapter.v
  24. +84
    -0
      k1g100k/rtl/LogicElement.v
  25. +137
    -0
      k1g100k/rtl/LogicTile.v
  26. +56
    -0
      k1g100k/rtl/LookUpTable.v
  27. +53
    -0
      k1g100k/rtl/Multiplexer.v
  28. +950
    -0
      k1g100k/rtl/SwitchBox.v
  29. +586142
    -0
      k1g100k/rtl/k1g100k.v
  30. +97
    -0
      k1g100k/techlib/cells.v
  31. +9
    -0
      k1g10k/k1g10k.kcf
  32. +58
    -0
      k1g10k/rtl/ConfigurationStorage.v
  33. +188
    -0
      k1g10k/rtl/IOAdapter.v
  34. +84
    -0
      k1g10k/rtl/LogicElement.v
  35. +137
    -0
      k1g10k/rtl/LogicTile.v
  36. +56
    -0
      k1g10k/rtl/LookUpTable.v
  37. +53
    -0
      k1g10k/rtl/Multiplexer.v
  38. +950
    -0
      k1g10k/rtl/SwitchBox.v
  39. +60194
    -0
      k1g10k/rtl/k1g10k.v
  40. +97
    -0
      k1g10k/techlib/cells.v
  41. +9
    -0
      k1g16/k1g16.kcf
  42. +58
    -0
      k1g16/rtl/ConfigurationStorage.v
  43. +156
    -0
      k1g16/rtl/IOAdapter.v
  44. +84
    -0
      k1g16/rtl/LogicElement.v
  45. +137
    -0
      k1g16/rtl/LogicTile.v
  46. +56
    -0
      k1g16/rtl/LookUpTable.v
  47. +53
    -0
      k1g16/rtl/Multiplexer.v
  48. +846
    -0
      k1g16/rtl/SwitchBox.v
  49. +290
    -0
      k1g16/rtl/k1g16.v
  50. +97
    -0
      k1g16/techlib/cells.v
  51. +9
    -0
      k1g1M/k1g1M.kcf
  52. +58
    -0
      k1g1M/rtl/ConfigurationStorage.v
  53. +188
    -0
      k1g1M/rtl/IOAdapter.v
  54. +84
    -0
      k1g1M/rtl/LogicElement.v
  55. +137
    -0
      k1g1M/rtl/LogicTile.v
  56. +56
    -0
      k1g1M/rtl/LookUpTable.v
  57. +53
    -0
      k1g1M/rtl/Multiplexer.v
  58. +950
    -0
      k1g1M/rtl/SwitchBox.v
  59. +5776094
    -0
      k1g1M/rtl/k1g1M.v
  60. +97
    -0
      k1g1M/techlib/cells.v
  61. +9
    -0
      k1g1k/k1g1k.kcf
  62. +58
    -0
      k1g1k/rtl/ConfigurationStorage.v
  63. +188
    -0
      k1g1k/rtl/IOAdapter.v
  64. +84
    -0
      k1g1k/rtl/LogicElement.v
  65. +137
    -0
      k1g1k/rtl/LogicTile.v
  66. +56
    -0
      k1g1k/rtl/LookUpTable.v
  67. +53
    -0
      k1g1k/rtl/Multiplexer.v
  68. +950
    -0
      k1g1k/rtl/SwitchBox.v
  69. +6814
    -0
      k1g1k/rtl/k1g1k.v
  70. +97
    -0
      k1g1k/techlib/cells.v
  71. +9
    -0
      k1g200/k1g200.kcf
  72. +58
    -0
      k1g200/rtl/ConfigurationStorage.v
  73. +188
    -0
      k1g200/rtl/IOAdapter.v
  74. +84
    -0
      k1g200/rtl/LogicElement.v
  75. +137
    -0
      k1g200/rtl/LogicTile.v
  76. +56
    -0
      k1g200/rtl/LookUpTable.v
  77. +53
    -0
      k1g200/rtl/Multiplexer.v
  78. +950
    -0
      k1g200/rtl/SwitchBox.v
  79. +1585
    -0
      k1g200/rtl/k1g200.v
  80. +97
    -0
      k1g200/techlib/cells.v
  81. +9
    -0
      k1g200k/k1g200k.kcf
  82. +58
    -0
      k1g200k/rtl/ConfigurationStorage.v
  83. +188
    -0
      k1g200k/rtl/IOAdapter.v
  84. +84
    -0
      k1g200k/rtl/LogicElement.v
  85. +137
    -0
      k1g200k/rtl/LogicTile.v
  86. +56
    -0
      k1g200k/rtl/LookUpTable.v
  87. +53
    -0
      k1g200k/rtl/Multiplexer.v
  88. +950
    -0
      k1g200k/rtl/SwitchBox.v
  89. +1165790
    -0
      k1g200k/rtl/k1g200k.v
  90. +97
    -0
      k1g200k/techlib/cells.v
  91. +9
    -0
      k1g20k/k1g20k.kcf
  92. +58
    -0
      k1g20k/rtl/ConfigurationStorage.v
  93. +188
    -0
      k1g20k/rtl/IOAdapter.v
  94. +84
    -0
      k1g20k/rtl/LogicElement.v
  95. +137
    -0
      k1g20k/rtl/LogicTile.v
  96. +56
    -0
      k1g20k/rtl/LookUpTable.v
  97. +53
    -0
      k1g20k/rtl/Multiplexer.v
  98. +950
    -0
      k1g20k/rtl/SwitchBox.v
  99. +119729
    -0
      k1g20k/rtl/k1g20k.v
  100. +97
    -0
      k1g20k/techlib/cells.v

+ 9
- 0
k1g1/k1g1.kcf View File

@ -0,0 +1,9 @@
{
"width": 1,
"height": 1,
"io_pairs_count": 1,
"interconnect_pairs_count": 1,
"le_count": 1,
"lut_size": 2,
"name": "k1g1"
}

+ 58
- 0
k1g1/rtl/ConfigurationStorage.v View File

@ -0,0 +1,58 @@
// Copyright Jonathan Tremesaygues (2019 - 2020)
//
// Jonathan Tremesaygues <jonathan.tremesaygues@slaanesh.org>
//
// This software is a computer program whose purpose is to [describe
// functionalities and technical features of your software].
//
// This software is governed by the CeCILL-B license under French law and
// abiding by the rules of distribution of free software. You can use,
// modify and/ or redistribute the software under the terms of the CeCILL-B
// license as circulated by CEA, CNRS and INRIA at the following URL
// "http://www.cecill.info".
//
// As a counterpart to the access to the source code and rights to copy,
// modify and redistribute granted by the license, users are provided only
// with a limited warranty and the software's author, the holder of the
// economic rights, and the successive licensors have only limited
// liability.
//
// In this respect, the user's attention is drawn to the risks associated
// with loading, using, modifying and/or developing or reproducing the
// software by the user in light of its specific status of free software,
// that may mean that it is complicated to manipulate, and that also
// therefore means that it is reserved for developers and experienced
// professionals having in-depth computer knowledge. Users are therefore
// encouraged to load and test the software's suitability as regards their
// requirements in conditions enabling the security of their systems and/or
// data to be ensured and, more generally, to use and operate it in the
// same conditions as regards security.
//
// The fact that you are presently reading this means that you have had
// knowledge of the CeCILL-B license and that you accept its terms.
// This file was generated by kfpga-generate-rtl
`timescale 1ns / 1ps
/**
* Configuration storage
*
* @tparam SIZE: Size of the configuration storage
* @param o_config: Output parallel configuratior
* @param i_config: Input serial configuration
* @param i_config_clk: Clock signal
* @param i_config_enable: Enable signal
*/
module ConfigurationStorage #(parameter SIZE = 8) (
output reg [SIZE - 1:0] o_config,
input i_config,
input i_config_clk,
input i_config_enable
);
always @(posedge i_config_clk) begin
if (i_config_enable) begin
o_config <= {o_config[SIZE - 2:0], i_config};
end
end
endmodule

+ 69
- 0
k1g1/rtl/IOAdapter.v View File

@ -0,0 +1,69 @@
// Copyright Jonathan Tremesaygues (2019 - 2020)
//
// Jonathan Tremesaygues <jonathan.tremesaygues@slaanesh.org>
//
// This software is a computer program whose purpose is to [describe
// functionalities and technical features of your software].
//
// This software is governed by the CeCILL-B license under French law and
// abiding by the rules of distribution of free software. You can use,
// modify and/ or redistribute the software under the terms of the CeCILL-B
// license as circulated by CEA, CNRS and INRIA at the following URL
// "http://www.cecill.info".
//
// As a counterpart to the access to the source code and rights to copy,
// modify and redistribute granted by the license, users are provided only
// with a limited warranty and the software's author, the holder of the
// economic rights, and the successive licensors have only limited
// liability.
//
// In this respect, the user's attention is drawn to the risks associated
// with loading, using, modifying and/or developing or reproducing the
// software by the user in light of its specific status of free software,
// that may mean that it is complicated to manipulate, and that also
// therefore means that it is reserved for developers and experienced
// professionals having in-depth computer knowledge. Users are therefore
// encouraged to load and test the software's suitability as regards their
// requirements in conditions enabling the security of their systems and/or
// data to be ensured and, more generally, to use and operate it in the
// same conditions as regards security.
//
// The fact that you are presently reading this means that you have had
// knowledge of the CeCILL-B license and that you accept its terms.
// This file was generated by kfpga-generate-rtl
`timescale 1ns / 1ps
/**
* An I/O adapter
*
* @param o_data_to_io: Data outgoing to I/O pads
* @param o_data_to_ic: Data outgoing to interconnect
* @param i_data_from_io: Data incoming from I/O pads
* @param i_data_from_ic: Data incomming from interconnect
* @param o_config: Output port of configuration
* @param i_config: Input port for configuration
* @param i_config_clk: Clock signal for the configuration
* @param i_config_enable: Enable signal for the configuration
* If high, the tile is on configuration mode, else on running mode
*/
module IOAdapter(
output o_data_to_io,
output o_data_to_ic,
input i_data_from_io,
input i_data_from_ic,
output o_config,
input i_config,
input i_config_clk,
input i_config_enable
);
// No config to store, pass-through
assign o_config = i_config;
// To I/O data selectors
assign o_data_to_io = i_data_from_ic;
// To interconnect data selectors
assign o_data_to_ic = i_data_from_io;
endmodule

+ 84
- 0
k1g1/rtl/LogicElement.v View File

@ -0,0 +1,84 @@
// Copyright Jonathan Tremesaygues (2019 - 2020)
//
// Jonathan Tremesaygues <jonathan.tremesaygues@slaanesh.org>
//
// This software is a computer program whose purpose is to [describe
// functionalities and technical features of your software].
//
// This software is governed by the CeCILL-B license under French law and
// abiding by the rules of distribution of free software. You can use,
// modify and/ or redistribute the software under the terms of the CeCILL-B
// license as circulated by CEA, CNRS and INRIA at the following URL
// "http://www.cecill.info".
//
// As a counterpart to the access to the source code and rights to copy,
// modify and redistribute granted by the license, users are provided only
// with a limited warranty and the software's author, the holder of the
// economic rights, and the successive licensors have only limited
// liability.
//
// In this respect, the user's attention is drawn to the risks associated
// with loading, using, modifying and/or developing or reproducing the
// software by the user in light of its specific status of free software,
// that may mean that it is complicated to manipulate, and that also
// therefore means that it is reserved for developers and experienced
// professionals having in-depth computer knowledge. Users are therefore
// encouraged to load and test the software's suitability as regards their
// requirements in conditions enabling the security of their systems and/or
// data to be ensured and, more generally, to use and operate it in the
// same conditions as regards security.
//
// The fact that you are presently reading this means that you have had
// knowledge of the CeCILL-B license and that you accept its terms.
// This file was generated by kfpga-generate-rtl
`timescale 1ns / 1ps
/**
* A logic element
*
* @param o_data: The output data
* @param i_data: The input data
* @param i_clock: The clock signal
* @param i_reset: The reset signal
*/
module LogicElement(
output o_data,
input [1:0] i_data,
input i_clock,
input i_reset,
input [4:0] i_config
);
// The LUT
wire w_lut_data;
LookUpTable c_lut(
.o_data(w_lut_data),
.i_data(i_data),
.i_config(i_config[3:0])
);
// The DFF
reg w_dff_data;
always @(posedge i_clock) begin
if (i_reset) begin
w_dff_data <= 1'b0;
end
else begin
w_dff_data <= w_lut_data;
end
end
// Choose between the LUT data and the DFF data
Multiplexer #(
.DATA_WIDTH(2),
.SELECTOR_WIDTH(1)
) c_data_selector(
.o_data(o_data),
.i_data({
w_dff_data,
w_lut_data
}),
.i_selector(i_config[4])
);
endmodule

+ 110
- 0
k1g1/rtl/LogicTile.v View File

@ -0,0 +1,110 @@
// Copyright Jonathan Tremesaygues (2019 - 2020)
//
// Jonathan Tremesaygues <jonathan.tremesaygues@slaanesh.org>
//
// This software is a computer program whose purpose is to [describe
// functionalities and technical features of your software].
//
// This software is governed by the CeCILL-B license under French law and
// abiding by the rules of distribution of free software. You can use,
// modify and/ or redistribute the software under the terms of the CeCILL-B
// license as circulated by CEA, CNRS and INRIA at the following URL
// "http://www.cecill.info".
//
// As a counterpart to the access to the source code and rights to copy,
// modify and redistribute granted by the license, users are provided only
// with a limited warranty and the software's author, the holder of the
// economic rights, and the successive licensors have only limited
// liability.
//
// In this respect, the user's attention is drawn to the risks associated
// with loading, using, modifying and/or developing or reproducing the
// software by the user in light of its specific status of free software,
// that may mean that it is complicated to manipulate, and that also
// therefore means that it is reserved for developers and experienced
// professionals having in-depth computer knowledge. Users are therefore
// encouraged to load and test the software's suitability as regards their
// requirements in conditions enabling the security of their systems and/or
// data to be ensured and, more generally, to use and operate it in the
// same conditions as regards security.
//
// The fact that you are presently reading this means that you have had
// knowledge of the CeCILL-B license and that you accept its terms.
// This file was generated by kfpga-generate-rtl
`timescale 1ns / 1ps
/**
* A logic tile
*
* @param i_data_north: Input data incomming from north side
* @param i_data_east: Input data incomming from east side
* @param i_data_south: Input data incomming from south side
* @param i_data_west: Input data incomming from west side
* @param o_data_north: Output data outgoing to north side
* @param o_data_east: Output data outgoing to east side
* @param o_data_south: Output data outgoing to south side
* @param o_data_west: Output data outgoing to west side
* @param i_clock: Clock signal
* @param i_reset: Reset signal
* @param i_config: Input port for configuration
* @param o_config: Output port of configuration
* @param i_config_clk: Clock signal for the configuration
* @param i_config_enable: Enable signal for the configuration
* If high, the tile is on configuration mode, else on running mode
*/
module LogicTile(
output o_data_north,
output o_data_east,
output o_data_south,
output o_data_west,
input i_data_north,
input i_data_east,
input i_data_south,
input i_data_west,
input i_clock,
input i_reset,
output o_config,
input i_config,
input i_config_clk,
input i_config_enable
);
// Configuration storage
wire [18:0] w_config;
ConfigurationStorage #(
.SIZE(19)
) c_configuration_storage(
.o_config(w_config),
.i_config(i_config),
.i_config_clk(i_config_clk),
.i_config_enable(i_config_enable)
);
assign o_config = w_config[18];
// Switch box
wire w_data_from_logic;
wire [1:0] w_data_to_logic;
SwitchBox c_switch_box(
.i_data_from_north(i_data_north),
.i_data_from_east(i_data_east),
.i_data_from_south(i_data_south),
.i_data_from_west(i_data_west),
.o_data_to_north(o_data_north),
.o_data_to_east(o_data_east),
.o_data_to_south(o_data_south),
.o_data_to_west(o_data_west),
.i_data_from_logic(w_data_from_logic),
.o_data_to_logic(w_data_to_logic),
.i_config(w_config[18:5])
);
// Logic element 0
LogicElement c_logic_element_0(
.o_data(w_data_from_logic),
.i_data(w_data_to_logic),
.i_clock(i_clock),
.i_reset(i_reset),
.i_config(w_config[4:0])
);
endmodule

+ 52
- 0
k1g1/rtl/LookUpTable.v View File

@ -0,0 +1,52 @@
// Copyright Jonathan Tremesaygues (2019 - 2020)
//
// Jonathan Tremesaygues <jonathan.tremesaygues@slaanesh.org>
//
// This software is a computer program whose purpose is to [describe
// functionalities and technical features of your software].
//
// This software is governed by the CeCILL-B license under French law and
// abiding by the rules of distribution of free software. You can use,
// modify and/ or redistribute the software under the terms of the CeCILL-B
// license as circulated by CEA, CNRS and INRIA at the following URL
// "http://www.cecill.info".
//
// As a counterpart to the access to the source code and rights to copy,
// modify and redistribute granted by the license, users are provided only
// with a limited warranty and the software's author, the holder of the
// economic rights, and the successive licensors have only limited
// liability.
//
// In this respect, the user's attention is drawn to the risks associated
// with loading, using, modifying and/or developing or reproducing the
// software by the user in light of its specific status of free software,
// that may mean that it is complicated to manipulate, and that also
// therefore means that it is reserved for developers and experienced
// professionals having in-depth computer knowledge. Users are therefore
// encouraged to load and test the software's suitability as regards their
// requirements in conditions enabling the security of their systems and/or
// data to be ensured and, more generally, to use and operate it in the
// same conditions as regards security.
//
// The fact that you are presently reading this means that you have had
// knowledge of the CeCILL-B license and that you accept its terms.
// This file was generated by kfpga-generate-rtl
`timescale 1ns / 1ps
/**
* A look-up table
*
* param o_data: Output data
* param i_data: Input data
* param i_config: Configuration of the LUT
*/
module LookUpTable(
output o_data,
input [1:0] i_data,
input [3:0] i_config
);
wire [1:0] s1 = i_data[1] ? i_config[3:2] : i_config[1:0];
assign o_data = i_data[0] ? s1[1] : s1[0];
endmodule

+ 53
- 0
k1g1/rtl/Multiplexer.v View File

@ -0,0 +1,53 @@
// Copyright Jonathan Tremesaygues (2019 - 2020)
//
// Jonathan Tremesaygues <jonathan.tremesaygues@slaanesh.org>
//
// This software is a computer program whose purpose is to [describe
// functionalities and technical features of your software].
//
// This software is governed by the CeCILL-B license under French law and
// abiding by the rules of distribution of free software. You can use,
// modify and/ or redistribute the software under the terms of the CeCILL-B
// license as circulated by CEA, CNRS and INRIA at the following URL
// "http://www.cecill.info".
//
// As a counterpart to the access to the source code and rights to copy,
// modify and redistribute granted by the license, users are provided only
// with a limited warranty and the software's author, the holder of the
// economic rights, and the successive licensors have only limited
// liability.
//
// In this respect, the user's attention is drawn to the risks associated
// with loading, using, modifying and/or developing or reproducing the
// software by the user in light of its specific status of free software,
// that may mean that it is complicated to manipulate, and that also
// therefore means that it is reserved for developers and experienced
// professionals having in-depth computer knowledge. Users are therefore
// encouraged to load and test the software's suitability as regards their
// requirements in conditions enabling the security of their systems and/or
// data to be ensured and, more generally, to use and operate it in the
// same conditions as regards security.
//
// The fact that you are presently reading this means that you have had
// knowledge of the CeCILL-B license and that you accept its terms.
// This file was generated by kfpga-generate-rtl
`timescale 1ns / 1ps
/**
* A multiplexer
*
* @tparam DATA_WIDTH: Width of the input data port
* @param SELECTOR_WIDTH: Width of the selector port
* @param o_data: Selected data
* @param i_data: Input data
* @param i_selector: The selector
*/
module Multiplexer #(parameter DATA_WIDTH = 2, parameter SELECTOR_WIDTH = 1) (
output o_data,
input [DATA_WIDTH - 1:0] i_data,
input [SELECTOR_WIDTH - 1:0] i_selector
);
assign o_data = i_data[i_selector];
endmodule

+ 152
- 0
k1g1/rtl/SwitchBox.v View File

@ -0,0 +1,152 @@
// Copyright Jonathan Tremesaygues (2019 - 2020)
//
// Jonathan Tremesaygues <jonathan.tremesaygues@slaanesh.org>
//
// This software is a computer program whose purpose is to [describe
// functionalities and technical features of your software].
//
// This software is governed by the CeCILL-B license under French law and
// abiding by the rules of distribution of free software. You can use,
// modify and/ or redistribute the software under the terms of the CeCILL-B
// license as circulated by CEA, CNRS and INRIA at the following URL
// "http://www.cecill.info".
//
// As a counterpart to the access to the source code and rights to copy,
// modify and redistribute granted by the license, users are provided only
// with a limited warranty and the software's author, the holder of the
// economic rights, and the successive licensors have only limited
// liability.
//
// In this respect, the user's attention is drawn to the risks associated
// with loading, using, modifying and/or developing or reproducing the
// software by the user in light of its specific status of free software,
// that may mean that it is complicated to manipulate, and that also
// therefore means that it is reserved for developers and experienced
// professionals having in-depth computer knowledge. Users are therefore
// encouraged to load and test the software's suitability as regards their
// requirements in conditions enabling the security of their systems and/or
// data to be ensured and, more generally, to use and operate it in the
// same conditions as regards security.
//
// The fact that you are presently reading this means that you have had
// knowledge of the CeCILL-B license and that you accept its terms.
// This file was generated by kfpga-generate-rtl
`timescale 1ns / 1ps
/**
* A switch box
*
* @param i_data_from_north: Input data incomming from north side
* @param i_data_from_east: Input data incomming from east side
* @param i_data_from_south: Input data incomming from south side
* @param i_data_from_west: Input data incomming from west side
* @param o_data_to_north: Output data outgoing to north side
* @param o_data_to_east: Output data outgoing to east side
* @param o_data_to_south: Output data outgoing to south side
* @param o_data_to_west: Output data outgoing to west side
* @param i_data_from_logic: Data incomming from logic
* @param o_data_to_logic: Data outgoing to logic
* @param i_config: Configuration bus
*/
module SwitchBox(
output o_data_to_north,
output o_data_to_east,
output o_data_to_south,
output o_data_to_west,
output [1:0] o_data_to_logic,
input i_data_from_north,
input i_data_from_east,
input i_data_from_south,
input i_data_from_west,
input i_data_from_logic,
input [13:0] i_config
);
// Data selector to logic 0
Multiplexer #(
.DATA_WIDTH(5),
.SELECTOR_WIDTH(3)
) c_to_logic_0(
.o_data(o_data_to_logic[0]),
.i_data({
i_data_from_west,
i_data_from_south,
i_data_from_east,
i_data_from_north,
i_data_from_logic
}),
.i_selector(i_config[2:0])
);
// Data selector to logic 1
Multiplexer #(
.DATA_WIDTH(5),
.SELECTOR_WIDTH(3)
) c_to_logic_1(
.o_data(o_data_to_logic[1]),
.i_data({
i_data_from_west,
i_data_from_south,
i_data_from_east,
i_data_from_north,
i_data_from_logic
}),
.i_selector(i_config[5:3])
);
// Data selectors for side north
Multiplexer #(
.DATA_WIDTH(4),
.SELECTOR_WIDTH(2)
) c_north_0_data_selector(
.o_data(o_data_to_north),
.i_data({
i_data_from_west,
i_data_from_south,
i_data_from_east,
i_data_from_logic
}),
.i_selector(i_config[7:6])
);
// Data selectors for side east
Multiplexer #(
.DATA_WIDTH(4),
.SELECTOR_WIDTH(2)
) c_east_0_data_selector(
.o_data(o_data_to_east),
.i_data({
i_data_from_north,
i_data_from_west,
i_data_from_south,
i_data_from_logic
}),
.i_selector(i_config[9:8])
);
// Data selectors for side south
Multiplexer #(
.DATA_WIDTH(4),
.SELECTOR_WIDTH(2)
) c_south_0_data_selector(
.o_data(o_data_to_south),
.i_data({
i_data_from_east,
i_data_from_north,
i_data_from_west,
i_data_from_logic
}),
.i_selector(i_config[11:10])
);
// Data selectors for side west
Multiplexer #(
.DATA_WIDTH(4),
.SELECTOR_WIDTH(2)
) c_west_0_data_selector(
.o_data(o_data_to_west),
.i_data({
i_data_from_south,
i_data_from_east,
i_data_from_north,
i_data_from_logic
}),
.i_selector(i_config[13:12])
);
endmodule

+ 169
- 0
k1g1/rtl/k1g1.v View File

@ -0,0 +1,169 @@
// Copyright Jonathan Tremesaygues (2019 - 2020)
//
// Jonathan Tremesaygues <jonathan.tremesaygues@slaanesh.org>
//
// This software is a computer program whose purpose is to [describe
// functionalities and technical features of your software].
//
// This software is governed by the CeCILL-B license under French law and
// abiding by the rules of distribution of free software. You can use,
// modify and/ or redistribute the software under the terms of the CeCILL-B
// license as circulated by CEA, CNRS and INRIA at the following URL
// "http://www.cecill.info".
//
// As a counterpart to the access to the source code and rights to copy,
// modify and redistribute granted by the license, users are provided only
// with a limited warranty and the software's author, the holder of the
// economic rights, and the successive licensors have only limited
// liability.
//
// In this respect, the user's attention is drawn to the risks associated
// with loading, using, modifying and/or developing or reproducing the
// software by the user in light of its specific status of free software,
// that may mean that it is complicated to manipulate, and that also
// therefore means that it is reserved for developers and experienced
// professionals having in-depth computer knowledge. Users are therefore
// encouraged to load and test the software's suitability as regards their
// requirements in conditions enabling the security of their systems and/or
// data to be ensured and, more generally, to use and operate it in the
// same conditions as regards security.
//
// The fact that you are presently reading this means that you have had
// knowledge of the CeCILL-B license and that you accept its terms.
// This file was generated by kfpga-generate-rtl
`timescale 1ns / 1ps
/**
* A kFPGA core
*
* @param o_data_north: Output data outgoing to north side
* @param o_data_east: Output data outgoing to east side
* @param o_data_south: Output data outgoing to south side
* @param o_data_west: Output data outgoing to west side
* @param i_data_north: Input data incomming from north side
* @param i_data_east: Input data incomming from east side
* @param i_data_south: Input data incomming from south side
* @param i_data_west: Input data incomming from west side
* @param i_clock: Clock signal
* @param i_reset: Reset signal
* @param o_config: Output port of configuration
* @param i_config: Input port for configuration
* @param i_config_clk: Clock signal for the configuration
* @param i_config_enable: Enable signal for the configuration
* If high, the kFPGA is on configuration mode, else on running mode
*/
module k1g1(
output o_data_north,
output o_data_east,
output o_data_south,
output o_data_west,
input i_data_north,
input i_data_east,
input i_data_south,
input i_data_west,
input i_clock,
input i_reset,
output o_config,
input i_config,
input i_config_clk,
input i_config_enable
);
// Wires
wire w_config_from_io_adapter_north_0;
wire w_data_from_io_adapter_north_0;
wire w_data_from_io_adapter_east_0;
wire w_config_from_io_adapter_south_0;
wire w_data_from_io_adapter_south_0;
wire w_config_from_io_adapter_west_0;
wire w_data_from_io_adapter_west_0;
wire w_config_from_tile_x0_y0;
wire w_data_north_from_tile_x0_y0;
wire w_data_east_from_tile_x0_y0;
wire w_data_south_from_tile_x0_y0;
wire w_data_west_from_tile_x0_y0;
//////////////////////////////////////////////////////////////////////////
// I/O adapters north
//////////////////////////////////////////////////////////////////////////
IOAdapter c_io_adapter_north_0(
.o_data_to_io(o_data_north),
.i_data_from_io(i_data_north),
.o_data_to_ic(w_data_from_io_adapter_north_0),
.i_data_from_ic(w_data_north_from_tile_x0_y0),
.o_config(w_config_from_io_adapter_north_0),
.i_config(w_config_from_tile_x0_y0),
.i_config_clk(i_config_clk),
.i_config_enable(i_config_enable)
);
//////////////////////////////////////////////////////////////////////////
// I/O adapters east
//////////////////////////////////////////////////////////////////////////
IOAdapter c_io_adapter_east_0(
.o_data_to_io(o_data_east),
.i_data_from_io(i_data_east),
.o_data_to_ic(w_data_from_io_adapter_east_0),
.i_data_from_ic(w_data_east_from_tile_x0_y0),
.o_config(o_config),
.i_config(w_config_from_io_adapter_north_0),
.i_config_clk(i_config_clk),
.i_config_enable(i_config_enable)
);
//////////////////////////////////////////////////////////////////////////
// I/O adapters south
//////////////////////////////////////////////////////////////////////////
IOAdapter c_io_adapter_south_0(
.o_data_to_io(o_data_south),
.i_data_from_io(i_data_south),
.o_data_to_ic(w_data_from_io_adapter_south_0),
.i_data_from_ic(w_data_south_from_tile_x0_y0),
.o_config(w_config_from_io_adapter_south_0),
.i_config(w_config_from_io_adapter_west_0),
.i_config_clk(i_config_clk),
.i_config_enable(i_config_enable)
);
//////////////////////////////////////////////////////////////////////////
// I/O adapters west
//////////////////////////////////////////////////////////////////////////
IOAdapter c_io_adapter_west_0(
.o_data_to_io(o_data_west),
.i_data_from_io(i_data_west),
.o_data_to_ic(w_data_from_io_adapter_west_0),
.i_data_from_ic(w_data_west_from_tile_x0_y0),
.o_config(w_config_from_io_adapter_west_0),
.i_config(i_config),
.i_config_clk(i_config_clk),
.i_config_enable(i_config_enable)
);
//////////////////////////////////////////////////////////////////////////
// Tiles
//////////////////////////////////////////////////////////////////////////
// Tile (0, 0)
LogicTile c_tile_x0_y0(
.o_data_north(w_data_north_from_tile_x0_y0),
.o_data_east(w_data_east_from_tile_x0_y0),
.o_data_south(w_data_south_from_tile_x0_y0),
.o_data_west(w_data_west_from_tile_x0_y0),
.i_data_north(w_data_from_io_adapter_north_0),
.i_data_east(w_data_from_io_adapter_east_0),
.i_data_south(w_data_from_io_adapter_south_0),
.i_data_west(w_data_from_io_adapter_west_0),
.i_clock(i_clock),
.i_reset(i_reset),
.o_config(w_config_from_tile_x0_y0),
.i_config(w_config_from_io_adapter_south_0),
.i_config_clk(i_config_clk),
.i_config_enable(i_config_enable)
);
endmodule

+ 93
- 0
k1g1/techlib/cells.v View File

@ -0,0 +1,93 @@
// Copyright Jonathan Tremesaygues (2019 - 2020)
//
// Jonathan Tremesaygues <jonathan.tremesaygues@slaanesh.org>
//
// This software is a computer program whose purpose is to [describe
// functionalities and technical features of your software].
//
// This software is governed by the CeCILL-B license under French law and
// abiding by the rules of distribution of free software. You can use,
// modify and/ or redistribute the software under the terms of the CeCILL-B
// license as circulated by CEA, CNRS and INRIA at the following URL
// "http://www.cecill.info".
//
// As a counterpart to the access to the source code and rights to copy,
// modify and redistribute granted by the license, users are provided only
// with a limited warranty and the software's author, the holder of the
// economic rights, and the successive licensors have only limited
// liability.
//
// In this respect, the user's attention is drawn to the risks associated
// with loading, using, modifying and/or developing or reproducing the
// software by the user in light of its specific status of free software,
// that may mean that it is complicated to manipulate, and that also
// therefore means that it is reserved for developers and experienced
// professionals having in-depth computer knowledge. Users are therefore
// encouraged to load and test the software's suitability as regards their
// requirements in conditions enabling the security of their systems and/or
// data to be ensured and, more generally, to use and operate it in the
// same conditions as regards security.
//
// The fact that you are presently reading this means that you have had
// knowledge of the CeCILL-B license and that you accept its terms.
// This file was generated by kfpga-generate-rtl
`timescale 1ns / 1ps
/**
* A DFF
*
* @param o_data: Output data
* @param i_data: Input data
* @param i_clock: Clock signal
* @param i_reset: Asynchronous reset signal, active on high
*/
module KTECH_DFF(o_data, i_data, i_clock);
output reg o_data;
input i_data, i_clock;
always @(posedge i_clock) begin
o_data <= i_data;
end
endmodule
/**
* A DFF with reset signal
*
* @param o_data: Output data
* @param i_data: Input data
* @param i_clock: Clock signal
* @param i_reset: Asynchronous reset signal, active on high
*/
module KTECH_DFFR(o_data, i_data, i_clock, i_reset);
output reg o_data;
input i_data, i_clock, i_reset;
always @(posedge i_clock, posedge i_reset) begin
if (i_reset) begin
o_data <= 1'b0;
end
else begin
o_data <= i_data;
end
end
endmodule
/**
* A LUT
*
* @tparam CONFIG: Configuration of the LUT
* @param o_data: Output data
* @param i_data: Input data
*/
module KTECH_LUT2(o_data, i_data);
parameter [3:0] CONFIG = 4'h0;
output o_data;
input [1:0] i_data;
wire [1:0] s1 = i_data[1] ? CONFIG[3:2] : CONFIG[1:0];
assign o_data = i_data[0] ? s1[1] : s1[0];
endmodule

+ 9
- 0
k1g100/k1g100.kcf View File

@ -0,0 +1,9 @@
{
"width": 5,
"height": 5,
"io_pairs_count": 4,
"interconnect_pairs_count": 10,
"le_count": 4,
"lut_size": 6,
"name": "k1g100"
}

+ 58
- 0
k1g100/rtl/ConfigurationStorage.v View File

@ -0,0 +1,58 @@
// Copyright Jonathan Tremesaygues (2019 - 2020)
//
// Jonathan Tremesaygues <jonathan.tremesaygues@slaanesh.org>
//
// This software is a computer program whose purpose is to [describe
// functionalities and technical features of your software].
//
// This software is governed by the CeCILL-B license under French law and
// abiding by the rules of distribution of free software. You can use,
// modify and/ or redistribute the software under the terms of the CeCILL-B
// license as circulated by CEA, CNRS and INRIA at the following URL
// "http://www.cecill.info".
//
// As a counterpart to the access to the source code and rights to copy,
// modify and redistribute granted by the license, users are provided only
// with a limited warranty and the software's author, the holder of the
// economic rights, and the successive licensors have only limited
// liability.
//
// In this respect, the user's attention is drawn to the risks associated
// with loading, using, modifying and/or developing or reproducing the
// software by the user in light of its specific status of free software,
// that may mean that it is complicated to manipulate, and that also
// therefore means that it is reserved for developers and experienced
// professionals having in-depth computer knowledge. Users are therefore
// encouraged to load and test the software's suitability as regards their
// requirements in conditions enabling the security of their systems and/or
// data to be ensured and, more generally, to use and operate it in the
// same conditions as regards security.
//
// The fact that you are presently reading this means that you have had
// knowledge of the CeCILL-B license and that you accept its terms.
// This file was generated by kfpga-generate-rtl
`timescale 1ns / 1ps
/**
* Configuration storage
*
* @tparam SIZE: Size of the configuration storage
* @param o_config: Output parallel configuratior
* @param i_config: Input serial configuration
* @param i_config_clk: Clock signal
* @param i_config_enable: Enable signal
*/
module ConfigurationStorage #(parameter SIZE = 8) (
output reg [SIZE - 1:0] o_config,
input i_config,
input i_config_clk,
input i_config_enable
);
always @(posedge i_config_clk) begin
if (i_config_enable) begin
o_config <= {o_config[SIZE - 2:0], i_config};
end
end
endmodule

+ 188
- 0
k1g100/rtl/IOAdapter.v View File

@ -0,0 +1,188 @@
// Copyright Jonathan Tremesaygues (2019 - 2020)
//
// Jonathan Tremesaygues <jonathan.tremesaygues@slaanesh.org>
//
// This software is a computer program whose purpose is to [describe
// functionalities and technical features of your software].
//
// This software is governed by the CeCILL-B license under French law and
// abiding by the rules of distribution of free software. You can use,
// modify and/ or redistribute the software under the terms of the CeCILL-B
// license as circulated by CEA, CNRS and INRIA at the following URL
// "http://www.cecill.info".
//
// As a counterpart to the access to the source code and rights to copy,
// modify and redistribute granted by the license, users are provided only
// with a limited warranty and the software's author, the holder of the
// economic rights, and the successive licensors have only limited
// liability.
//
// In this respect, the user's attention is drawn to the risks associated
// with loading, using, modifying and/or developing or reproducing the
// software by the user in light of its specific status of free software,
// that may mean that it is complicated to manipulate, and that also
// therefore means that it is reserved for developers and experienced
// professionals having in-depth computer knowledge. Users are therefore
// encouraged to load and test the software's suitability as regards their
// requirements in conditions enabling the security of their systems and/or
// data to be ensured and, more generally, to use and operate it in the
// same conditions as regards security.
//
// The fact that you are presently reading this means that you have had
// knowledge of the CeCILL-B license and that you accept its terms.
// This file was generated by kfpga-generate-rtl
`timescale 1ns / 1ps
/**
* An I/O adapter
*
* @param o_data_to_io: Data outgoing to I/O pads
* @param o_data_to_ic: Data outgoing to interconnect
* @param i_data_from_io: Data incoming from I/O pads
* @param i_data_from_ic: Data incomming from interconnect
* @param o_config: Output port of configuration
* @param i_config: Input port for configuration
* @param i_config_clk: Clock signal for the configuration
* @param i_config_enable: Enable signal for the configuration
* If high, the tile is on configuration mode, else on running mode
*/
module IOAdapter(
output [3:0] o_data_to_io,
output [9:0] o_data_to_ic,
input [3:0] i_data_from_io,
input [9:0] i_data_from_ic,
output o_config,
input i_config,
input i_config_clk,
input i_config_enable
);
// Configuration storage
wire [35:0] w_config;
ConfigurationStorage #(
.SIZE(36)
) c_configuration_storage(
.o_config(w_config),
.i_config(i_config),
.i_config_clk(i_config_clk),
.i_config_enable(i_config_enable)
);
assign o_config = w_config[35];
// To I/O data selectors
Multiplexer #(
.DATA_WIDTH(10),
.SELECTOR_WIDTH(4)
) c_to_io_0 (
.o_data(o_data_to_io[0]),
.i_data(i_data_from_ic),
.i_selector(w_config[3:0])
);
Multiplexer #(
.DATA_WIDTH(10),
.SELECTOR_WIDTH(4)
) c_to_io_1 (
.o_data(o_data_to_io[1]),
.i_data(i_data_from_ic),
.i_selector(w_config[7:4])
);
Multiplexer #(
.DATA_WIDTH(10),
.SELECTOR_WIDTH(4)
) c_to_io_2 (
.o_data(o_data_to_io[2]),
.i_data(i_data_from_ic),
.i_selector(w_config[11:8])
);
Multiplexer #(
.DATA_WIDTH(10),
.SELECTOR_WIDTH(4)
) c_to_io_3 (
.o_data(o_data_to_io[3]),
.i_data(i_data_from_ic),
.i_selector(w_config[15:12])
);
// To interconnect data selectors
Multiplexer #(
.DATA_WIDTH(4),
.SELECTOR_WIDTH(2)
) c_to_ic_0 (
.o_data(o_data_to_ic[0]),
.i_data(i_data_from_io),
.i_selector(w_config[17:16])
);
Multiplexer #(
.DATA_WIDTH(4),
.SELECTOR_WIDTH(2)
) c_to_ic_1 (
.o_data(o_data_to_ic[1]),
.i_data(i_data_from_io),
.i_selector(w_config[19:18])
);
Multiplexer #(
.DATA_WIDTH(4),
.SELECTOR_WIDTH(2)
) c_to_ic_2 (
.o_data(o_data_to_ic[2]),
.i_data(i_data_from_io),
.i_selector(w_config[21:20])
);
Multiplexer #(
.DATA_WIDTH(4),
.SELECTOR_WIDTH(2)
) c_to_ic_3 (
.o_data(o_data_to_ic[3]),
.i_data(i_data_from_io),
.i_selector(w_config[23:22])
);
Multiplexer #(
.DATA_WIDTH(4),
.SELECTOR_WIDTH(2)
) c_to_ic_4 (
.o_data(o_data_to_ic[4]),
.i_data(i_data_from_io),
.i_selector(w_config[25:24])
);
Multiplexer #(
.DATA_WIDTH(4),
.SELECTOR_WIDTH(2)
) c_to_ic_5 (
.o_data(o_data_to_ic[5]),
.i_data(i_data_from_io),
.i_selector(w_config[27:26])
);
Multiplexer #(
.DATA_WIDTH(4),
.SELECTOR_WIDTH(2)
) c_to_ic_6 (
.o_data(o_data_to_ic[6]),
.i_data(i_data_from_io),
.i_selector(w_config[29:28])
);
Multiplexer #(
.DATA_WIDTH(4),
.SELECTOR_WIDTH(2)
) c_to_ic_7 (
.o_data(o_data_to_ic[7]),
.i_data(i_data_from_io),
.i_selector(w_config[31:30])
);
Multiplexer #(
.DATA_WIDTH(4),
.SELECTOR_WIDTH(2)
) c_to_ic_8 (
.o_data(o_data_to_ic[8]),
.i_data(i_data_from_io),
.i_selector(w_config[33:32])
);
Multiplexer #(
.DATA_WIDTH(4),
.SELECTOR_WIDTH(2)
) c_to_ic_9 (
.o_data(o_data_to_ic[9]),
.i_data(i_data_from_io),
.i_selector(w_config[35:34])
);
endmodule

+ 84
- 0
k1g100/rtl/LogicElement.v View File

@ -0,0 +1,84 @@
// Copyright Jonathan Tremesaygues (2019 - 2020)
//
// Jonathan Tremesaygues <jonathan.tremesaygues@slaanesh.org>
//
// This software is a computer program whose purpose is to [describe
// functionalities and technical features of your software].
//
// This software is governed by the CeCILL-B license under French law and
// abiding by the rules of distribution of free software. You can use,
// modify and/ or redistribute the software under the terms of the CeCILL-B
// license as circulated by CEA, CNRS and INRIA at the following URL
// "http://www.cecill.info".
//
// As a counterpart to the access to the source code and rights to copy,
// modify and redistribute granted by the license, users are provided only
// with a limited warranty and the software's author, the holder of the
// economic rights, and the successive licensors have only limited
// liability.
//
// In this respect, the user's attention is drawn to the risks associated
// with loading, using, modifying and/or developing or reproducing the
// software by the user in light of its specific status of free software,
// that may mean that it is complicated to manipulate, and that also
// therefore means that it is reserved for developers and experienced
// professionals having in-depth computer knowledge. Users are therefore
// encouraged to load and test the software's suitability as regards their
// requirements in conditions enabling the security of their systems and/or
// data to be ensured and, more generally, to use and operate it in the
// same conditions as regards security.
//
// The fact that you are presently reading this means that you have had
// knowledge of the CeCILL-B license and that you accept its terms.
// This file was generated by kfpga-generate-rtl
`timescale 1ns / 1ps
/**
* A logic element
*
* @param o_data: The output data
* @param i_data: The input data
* @param i_clock: The clock signal
* @param i_reset: The reset signal
*/
module LogicElement(
output o_data,
input [5:0] i_data,
input i_clock,
input i_reset,
input [64:0] i_config
);
// The LUT
wire w_lut_data;
LookUpTable c_lut(
.o_data(w_lut_data),
.i_data(i_data),
.i_config(i_config[63:0])
);
// The DFF
reg w_dff_data;
always @(posedge i_clock) begin
if (i_reset) begin
w_dff_data <= 1'b0;
end
else begin
w_dff_data <= w_lut_data;
end
end
// Choose between the LUT data and the DFF data
Multiplexer #(
.DATA_WIDTH(2),
.SELECTOR_WIDTH(1)
) c_data_selector(
.o_data(o_data),
.i_data({
w_dff_data,
w_lut_data
}),
.i_selector(i_config[64])
);
endmodule

+ 137
- 0
k1g100/rtl/LogicTile.v View File

@ -0,0 +1,137 @@
// Copyright Jonathan Tremesaygues (2019 - 2020)
//
// Jonathan Tremesaygues <jonathan.tremesaygues@slaanesh.org>
//
// This software is a computer program whose purpose is to [describe
// functionalities and technical features of your software].
//
// This software is governed by the CeCILL-B license under French law and
// abiding by the rules of distribution of free software. You can use,
// modify and/ or redistribute the software under the terms of the CeCILL-B
// license as circulated by CEA, CNRS and INRIA at the following URL
// "http://www.cecill.info".
//
// As a counterpart to the access to the source code and rights to copy,
// modify and redistribute granted by the license, users are provided only
// with a limited warranty and the software's author, the holder of the
// economic rights, and the successive licensors have only limited
// liability.
//
// In this respect, the user's attention is drawn to the risks associated
// with loading, using, modifying and/or developing or reproducing the
// software by the user in light of its specific status of free software,
// that may mean that it is complicated to manipulate, and that also
// therefore means that it is reserved for developers and experienced
// professionals having in-depth computer knowledge. Users are therefore
// encouraged to load and test the software's suitability as regards their
// requirements in conditions enabling the security of their systems and/or
// data to be ensured and, more generally, to use and operate it in the
// same conditions as regards security.
//
// The fact that you are presently reading this means that you have had
// knowledge of the CeCILL-B license and that you accept its terms.
// This file was generated by kfpga-generate-rtl
`timescale 1ns / 1ps
/**
* A logic tile
*
* @param i_data_north: Input data incomming from north side
* @param i_data_east: Input data incomming from east side
* @param i_data_south: Input data incomming from south side
* @param i_data_west: Input data incomming from west side
* @param o_data_north: Output data outgoing to north side
* @param o_data_east: Output data outgoing to east side
* @param o_data_south: Output data outgoing to south side
* @param o_data_west: Output data outgoing to west side
* @param i_clock: Clock signal
* @param i_reset: Reset signal
* @param i_config: Input port for configuration
* @param o_config: Output port of configuration
* @param i_config_clk: Clock signal for the configuration
* @param i_config_enable: Enable signal for the configuration
* If high, the tile is on configuration mode, else on running mode
*/
module LogicTile(
output [9:0] o_data_north,
output [9:0] o_data_east,
output [9:0] o_data_south,
output [9:0] o_data_west,
input [9:0] i_data_north,
input [9:0] i_data_east,
input [9:0] i_data_south,
input [9:0] i_data_west,
input i_clock,
input i_reset,
output o_config,
input i_config,
input i_config_clk,
input i_config_enable
);
// Configuration storage
wire [523:0] w_config;
ConfigurationStorage #(
.SIZE(524)
) c_configuration_storage(
.o_config(w_config),
.i_config(i_config),
.i_config_clk(i_config_clk),
.i_config_enable(i_config_enable)
);
assign o_config = w_config[523];
// Switch box
wire [3:0] w_data_from_logic;
wire [23:0] w_data_to_logic;
SwitchBox c_switch_box(
.i_data_from_north(i_data_north),
.i_data_from_east(i_data_east),
.i_data_from_south(i_data_south),
.i_data_from_west(i_data_west),
.o_data_to_north(o_data_north),
.o_data_to_east(o_data_east),
.o_data_to_south(o_data_south),
.o_data_to_west(o_data_west),
.i_data_from_logic(w_data_from_logic),
.o_data_to_logic(w_data_to_logic),
.i_config(w_config[523:260])
);
// Logic element 0
LogicElement c_logic_element_0(
.o_data(w_data_from_logic[0]),
.i_data(w_data_to_logic[5:0]),
.i_clock(i_clock),
.i_reset(i_reset),
.i_config(w_config[64:0])
);
// Logic element 1
LogicElement c_logic_element_1(
.o_data(w_data_from_logic[1]),
.i_data(w_data_to_logic[11:6]),
.i_clock(i_clock),
.i_reset(i_reset),
.i_config(w_config[129:65])
);
// Logic element 2
LogicElement c_logic_element_2(
.o_data(w_data_from_logic[2]),
.i_data(w_data_to_logic[17:12]),
.i_clock(i_clock),
.i_reset(i_reset),
.i_config(w_config[194:130])
);
// Logic element 3
LogicElement c_logic_element_3(
.o_data(w_data_from_logic[3]),
.i_data(w_data_to_logic[23:18]),
.i_clock(i_clock),
.i_reset(i_reset),
.i_config(w_config[259:195])
);
endmodule

+ 56
- 0
k1g100/rtl/LookUpTable.v View File

@ -0,0 +1,56 @@
// Copyright Jonathan Tremesaygues (2019 - 2020)
//
// Jonathan Tremesaygues <jonathan.tremesaygues@slaanesh.org>
//
// This software is a computer program whose purpose is to [describe
// functionalities and technical features of your software].
//
// This software is governed by the CeCILL-B license under French law and
// abiding by the rules of distribution of free software. You can use,
// modify and/ or redistribute the software under the terms of the CeCILL-B
// license as circulated by CEA, CNRS and INRIA at the following URL
// "http://www.cecill.info".
//
// As a counterpart to the access to the source code and rights to copy,
// modify and redistribute granted by the license, users are provided only
// with a limited warranty and the software's author, the holder of the
// economic rights, and the successive licensors have only limited
// liability.
//
// In this respect, the user's attention is drawn to the risks associated
// with loading, using, modifying and/or developing or reproducing the
// software by the user in light of its specific status of free software,
// that may mean that it is complicated to manipulate, and that also
// therefore means that it is reserved for developers and experienced
// professionals having in-depth computer knowledge. Users are therefore
// encouraged to load and test the software's suitability as regards their
// requirements in conditions enabling the security of their systems and/or
// data to be ensured and, more generally, to use and operate it in the
// same conditions as regards security.
//
// The fact that you are presently reading this means that you have had
// knowledge of the CeCILL-B license and that you accept its terms.
// This file was generated by kfpga-generate-rtl
`timescale 1ns / 1ps
/**
* A look-up table
*
* param o_data: Output data
* param i_data: Input data
* param i_config: Configuration of the LUT
*/
module LookUpTable(
output o_data,
input [5:0] i_data,
input [63:0] i_config
);
wire [31:0] s5 = i_data[5] ? i_config[63:32] : i_config[31:0];
wire [15:0] s4 = i_data[4] ? s5[31:16] : s5[15:0];
wire [7:0] s3 = i_data[3] ? s4[15:8] : s4[7:0];
wire [3:0] s2 = i_data[2] ? s3[7:4] : s3[3:0];
wire [1:0] s1 = i_data[1] ? s2[3:2] : s2[1:0];
assign o_data = i_data[0] ? s1[1] : s1[0];
endmodule

+ 53
- 0
k1g100/rtl/Multiplexer.v View File

@ -0,0 +1,53 @@
// Copyright Jonathan Tremesaygues (2019 - 2020)
//
// Jonathan Tremesaygues <jonathan.tremesaygues@slaanesh.org>
//
// This software is a computer program whose purpose is to [describe
// functionalities and technical features of your software].
//
// This software is governed by the CeCILL-B license under French law and
// abiding by the rules of distribution of free software. You can use,
// modify and/ or redistribute the software under the terms of the CeCILL-B
// license as circulated by CEA, CNRS and INRIA at the following URL
// "http://www.cecill.info".
//
// As a counterpart to the access to the source code and rights to copy,
// modify and redistribute granted by the license, users are provided only
// with a limited warranty and the software's author, the holder of the
// economic rights, and the successive licensors have only limited
// liability.
//
// In this respect, the user's attention is drawn to the risks associated
// with loading, using, modifying and/or developing or reproducing the
// software by the user in light of its specific status of free software,
// that may mean that it is complicated to manipulate, and that also
// therefore means that it is reserved for developers and experienced
// professionals having in-depth computer knowledge. Users are therefore
// encouraged to load and test the software's suitability as regards their
// requirements in conditions enabling the security of their systems and/or
// data to be ensured and, more generally, to use and operate it in the
// same conditions as regards security.
//
// The fact that you are presently reading this means that you have had
// knowledge of the CeCILL-B license and that you accept its terms.
// This file was generated by kfpga-generate-rtl
`timescale 1ns / 1ps
/**
* A multiplexer
*
* @tparam DATA_WIDTH: Width of the input data port
* @param SELECTOR_WIDTH: Width of the selector port
* @param o_data: Selected data
* @param i_data: Input data
* @param i_selector: The selector
*/
module Multiplexer #(parameter DATA_WIDTH = 2, parameter SELECTOR_WIDTH = 1) (
output o_data,
input [DATA_WIDTH - 1:0] i_data,
input [SELECTOR_WIDTH - 1:0] i_selector
);
assign o_data = i_data[i_selector];
endmodule

+ 950
- 0
k1g100/rtl/SwitchBox.v View File

@ -0,0 +1,950 @@
// Copyright Jonathan Tremesaygues (2019 - 2020)
//
// Jonathan Tremesaygues <jonathan.tremesaygues@slaanesh.org>
//
// This software is a computer program whose purpose is to [describe
// functionalities and technical features of your software].
//
// This software is governed by the CeCILL-B license under French law and
// abiding by the rules of distribution of free software. You can use,
// modify and/ or redistribute the software under the terms of the CeCILL-B
// license as circulated by CEA, CNRS and INRIA at the following URL