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An open-source FPGA architecture and the tools needed for programming it.
$ git clone https://git.slaanesh.org/kfpga/kfpga.git
$ cd kfpga
$ python setup.py install
You also need the following tools:
This first iteration of the architecture is very simple. More functionalities are planned to be implemented in the next generations (see next title).
The architecture is composed of logic tiles of I/O adapters connecting the outer I/O pads of the FPGA to the routing network. Each FPGA has one clock signal and one reset signal.
Each logic tile is composed of a switch box used for doing the routing and
one or more logic element
Each logic element is composed of a LUT followed by a by-passable DFF.
All the LUT of a FPGA are of the same size.
The DFF are asynchronously resettables on positive edge. They don't support synchronous reset, set functionality or enable signal.
The following functionalities are planned to be implemented in the next generations of the architecture :
You can create a new kFPGA core with the kfpga-create-core
command. The command generate a .kcf
(kFPGA Core File) containing the description of the core. This file is needed by the majority of the others commands.
$ kfpga-create-core -h
usage: kfpga-create-core [-h] [--name NAME] width height io interconnect le lut core_file
Create a new core
positional arguments:
width Width of the core in number of logic tiles
height Height of the core in number of logic tiles
io Number of I/O pairs per side of border tiles
interconnect Number of interconnect pairs between tiles
le Number of logic elements per tile
lut Size of the LUTs
core_file The output core file
optional arguments:
-h, --help show this help message and exit
--name NAME Name of the core
Example :
$ kfpga-create-core --name k1g1k 16 16 4 10 4 6 k1g1k.kcf
Use the command kfpga-generate-rtl
for generating the RTL of a kFPGA core.
$ kfpga-generate-rtl -h
usage: kfpga-generate-rtl [-h] core_file rtl_dir
Generate the rtl of a core
positional arguments:
core_file The input core file
rtl_dir The output rtl directory
optional arguments:
-h, --help show this help message and exit
Example:
$ kfpga-generate-rtl k1g1k.kcf rtl
$ ls rtl
ConfigurationStorage.v IOAdapter.v k1g1k.v LogicElement.v LogicTile.v LookUpTable.v Multiplexer.v SwitchBox.v
Use the command kfpga-synthesize
for synthesizing a design. Yosys is used for doing the synthesis, so it must be installed.
$ kfpga-synthesize -h
usage: kfpga-synthesize [-h] [-y YOSYS] [-f] [-o OUTPUT] [-t TOP] core_file input_files [input_files ...]
Synthesize a design
positional arguments:
core_file The core .kcf file
input_files RTL files to synthesize
optional arguments:
-h, --help show this help message and exit
-y YOSYS, --yosys YOSYS
The yosys executable used for the synthesis
-f, --flatten Flatten the design
-o OUTPUT, --output OUTPUT
Output netlist
-t TOP, --top TOP The top to use
Example :
$ cat Adder2.v
module Adder2(z, a, b, clk);
output reg [2:0] z;
input [1:0] a, b;
input clk;
always @(posedge clk)
z <= a + b;
endmodule⏎
$ kfpga-synthesize -o Adder2_netlist.v k1g1k.kcf Adder.v
(SNIP)
$ cat Adder2_netlist.v
/* Generated by Yosys 0.9+2406 (git sha1 7c06cb61, gcc 9.3.0-1 -march=native -O3 -fno-plt -fPIC -Os) */
(* top = 1 *)
(* src = "Adder2.v:1.1-8.10" *)
module Adder2(z, a, b, clk);
(* src = "Adder2.v:3.17-3.18" *)
input [1:0] a;
(* src = "Adder2.v:3.20-3.21" *)
input [1:0] b;
(* src = "Adder2.v:4.11-4.14" *)
input clk;
(* src = "Adder2.v:2.22-2.23" *)
output [2:0] z;
(* src = "Adder2.v:6.5-7.20" *)
wire [2:0] z_KTECH_DFF_o_data_i_data;
(* module_not_derived = 32'd1 *)
(* src = "/tmp/tmpk524fkvb/cells_map.v:60.15-63.14" *)
KTECH_LUT6 #(
.CONFIG(64'h0000000000008778)
) a_KTECH_LUT6_i_data (
.i_data({ 2'h0, b[1], a[1], b[0], a[0] }),
.o_data(z_KTECH_DFF_o_data_i_data[1])
);
(* module_not_derived = 32'd1 *)
(* src = "/tmp/tmpk524fkvb/cells_map.v:60.15-63.14" *)
KTECH_LUT6 #(
.CONFIG(64'h000000000000e888)
) a_KTECH_LUT6_i_data_1 (
.i_data({ 2'h0, b[0], a[0], b[1], a[1] }),
.o_data(z_KTECH_DFF_o_data_i_data[2])
);
(* module_not_derived = 32'd1 *)
(* src = "/tmp/tmpk524fkvb/cells_map.v:44.15-47.14" *)
KTECH_LUT6 #(
.CONFIG(64'h0000000000000006)
) a_KTECH_LUT6_i_data_2 (
.i_data({ 4'h0, b[0], a[0] }),
.o_data(z_KTECH_DFF_o_data_i_data[0])
);
(* module_not_derived = 32'd1 *)
(* src = "Adder2.v:6.5-7.20|/tmp/tmpk524fkvb/cells_map.v:3.15-7.6" *)
KTECH_DFF z_KTECH_DFF_o_data (
.i_clock(clk),
.i_data(z_KTECH_DFF_o_data_i_data[2]),
.o_data(z[2])
);
(* module_not_derived = 32'd1 *)
(* src = "Adder2.v:6.5-7.20|/tmp/tmpk524fkvb/cells_map.v:3.15-7.6" *)
KTECH_DFF z_KTECH_DFF_o_data_1 (
.i_clock(clk),
.i_data(z_KTECH_DFF_o_data_i_data[1]),
.o_data(z[1])
);
(* module_not_derived = 32'd1 *)
(* src = "Adder2.v:6.5-7.20|/tmp/tmpk524fkvb/cells_map.v:3.15-7.6" *)
KTECH_DFF z_KTECH_DFF_o_data_2 (
.i_clock(clk),
.i_data(z_KTECH_DFF_o_data_i_data[0]),
.o_data(z[0])
);
endmodule
Use the command kfpga-generate-techlib
for generating the verilog cells library of core. The cell library is useful for testing or simulating a synthesized design.
$ kfpga-generate-techlib -h
usage: kfpga-generate-techlib [-h] core techlib
Generate the verilog techlib of a core
positional arguments:
core The input core file
techlib The output techlib file
optional arguments:
-h, --help show this help message and exit
Example:
$ kfpga-generate-techlib k1g1k.kcf techlib/cells.v