An opensource FPGA architecture
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README.md

killruana's FPGA (kFPGA)

Build Status

An open-source FPGA architecture and the tools needed for programming it.

Usage

Right now, there is no conveniant CLI or GUI tools for using kFPGA, only the API.

Create a core object

The core object represent a FPGA core. It is needed by virtually all useful API methods.

from kfpga.api import Core

core = Core(
    width=8,
    height=8,
    io_pairs_count=4,
    interconnect_pairs_count=16,
    le_count=4,
    lut_size=6,
    name="k1g256",
)

Generate the RTL (verilog) of a core

from pathlib import Path
from kfpga.api import generate_core_rtl

output_dir = Path("/path/to/output/rtl/folder")
generate_core_rtl(core, output_dir)

Architecture

Generation 1

This first iteration of the architecture is very simple. More functionalities are planned to be implemented in the next generations (see next title).

The architecture is composed of logic tiles of I/O adapters connecting the outer I/O pads of the FPGA to the routing network. Each FPGA has one clock signal and one reset signal.

Architecture overview

Each logic tile is composed of a switch box used for doing the routing and
one or more logic element

Logic tile overview

Each logic element is composed of a LUT followed by a by-passable DFF.

Logic element overview

All the LUT of a FPGA are the same size.

The DFF are asynchronously resettables on positive edge. They don't support synchronous reset, set functionality or enable signal.

The future

The following functionalities are planned to be implemented in the next generations of the architecture :

  • multiple external clock signals
  • multiple external set/reset signals
  • multiple external enable signals
  • DFF with set and reset functionality which can be synchronously or asynchronously asserted, an enable functionality
  • better logic elements with more functionality (like full-adder)
  • DSP blocks
  • memory blocks
  • support for generated clock, set, reset and enable signals