|Jonathan Tremesaygues 5146d75f9c||4 days ago|
|images||2 months ago|
|src/kfpga||4 days ago|
|tests||2 months ago|
|.gitignore||4 months ago|
|LICENSE.EN.txt||5 months ago|
|LICENSE.FR.txt||5 months ago|
|README.md||2 months ago|
|setup.py||2 weeks ago|
|tox.ini||4 months ago|
An open-source FPGA architecture and the tools needed for programming it.
Right now, there is no conveniant CLI or GUI tools for using kFPGA, only the API.
The core object represent a FPGA core. It is needed by virtually all useful API methods.
from kfpga.api import Core core = Core( width=8, height=8, io_pairs_count=4, interconnect_pairs_count=16, le_count=4, lut_size=6, name="k1g256", )
from pathlib import Path from kfpga.api import generate_core_rtl output_dir = Path("/path/to/output/rtl/folder") generate_core_rtl(core, output_dir)
This first iteration of the architecture is very simple. More functionalities are planned to be implemented in the next generations (see next title).
The architecture is composed of logic tiles of I/O adapters connecting the outer I/O pads of the FPGA to the routing network. Each FPGA has one clock signal and one reset signal.
Each logic tile is composed of a switch box used for doing the routing and
one or more logic element
Each logic element is composed of a LUT followed by a by-passable DFF.
All the LUT of a FPGA are the same size.
The DFF are asynchronously resettables on positive edge. They don't support synchronous reset, set functionality or enable signal.
The following functionalities are planned to be implemented in the next generations of the architecture :