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add a command for generating the cells techlib,

move generate_cells_map to synthesize module
master
parent
commit
b78b07093f
9 changed files with 109 additions and 51 deletions
  1. +23
    -0
      README.md
  2. +1
    -0
      setup.py
  3. +2
    -2
      src/kfpga/api.py
  4. +45
    -20
      src/kfpga/commands.py
  5. +33
    -8
      src/kfpga/synthesis.py
  6. +4
    -20
      src/kfpga/techlib.py
  7. +0
    -0
      src/kfpga/templates/synthesis/cells_map.v
  8. +1
    -1
      src/kfpga/templates/synthesis/synthesis.ys
  9. +0
    -0
      src/kfpga/templates/techlib/cells.v

+ 23
- 0
README.md View File

@ -213,4 +213,27 @@ module Adder2(z, a, b, clk);
.o_data(z[0])
);
endmodule
```
### Generating the cells library of a core
Use the command `kfpga-generate-techlib` for generating the verilog cells library of core. The cell library is useful for testing or simulating a synthesized design.
```
$ kfpga-generate-techlib -h
usage: kfpga-generate-techlib [-h] core techlib
Generate the verilog techlib of a core
positional arguments:
core The input core file
techlib The output techlib file
optional arguments:
-h, --help show this help message and exit
```
Example:
```
$ kfpga-generate-techlib k1g1k.kcf techlib/cells.v
```

+ 1
- 0
setup.py View File

@ -57,6 +57,7 @@ setuptools.setup(
"console_scripts": [
"kfpga-create-core=kfpga.commands:command_create_core",
"kfpga-generate-rtl=kfpga.commands:command_generate_rtl",
"kfpga-generate-techlib=kfpga.commands:command_generate_techlib",
"kfpga-synthesize=kfpga.commands:command_synthesize",
]
},


+ 2
- 2
src/kfpga/api.py View File

@ -33,5 +33,5 @@
from kfpga.io import load_core, save_core
from kfpga.hdl_core import generate_core_rtl
from kfpga.models import Core
from kfpga.synthesis import generate_synthesis_script
from kfpga.techlib import generate_cells_map, generate_cells_sim
from kfpga.synthesis import generate_cells_map, generate_synthesis_script
from kfpga.techlib import generate_techlib_cells

+ 45
- 20
src/kfpga/commands.py View File

@ -38,7 +38,7 @@ from typing import Iterable, Optional, Text
from kfpga.api import (
Core,
generate_cells_map,
generate_cells_sim,
generate_techlib_cells,
generate_core_rtl,
generate_synthesis_script,
load_core,
@ -76,7 +76,7 @@ def command_create_core(args: Optional[Iterable[Text]] = None) -> None:
"lut", type=int, help="Size of the LUTs",
)
arg_parser.add_argument(
"core_file", help="The output core file",
"core", help="The output core file",
)
args = arg_parser.parse_args(args)
@ -90,9 +90,9 @@ def command_create_core(args: Optional[Iterable[Text]] = None) -> None:
lut_size=args.lut,
)
core_file = Path(args.core_file)
core_file.parent.mkdir(mode=0o755, parents=True, exist_ok=True)
with core_file.open("w") as f:
core_path = Path(args.core)
core_path.parent.mkdir(mode=0o755, parents=True, exist_ok=True)
with core_path.open("w") as f:
save_core(core, f)
@ -105,22 +105,47 @@ def command_generate_rtl(args: Optional[Iterable[Text]] = None) -> None:
description="Generate the rtl of a core"
)
arg_parser.add_argument(
"core_file", help="The input core file",
"core", help="The input core file",
)
arg_parser.add_argument(
"rtl_dir", help="The output rtl directory",
"rtl", help="The output rtl directory",
)
args = arg_parser.parse_args(args)
core_file = Path(args.core_file)
with core_file.open() as f:
core_path = Path(args.core)
with core_path.open() as f:
core = load_core(f)
rtl_path = Path(args.rtl_dir)
rtl_path = Path(args.rtl)
generate_core_rtl(core, rtl_path)
def command_generate_techlib(args: Optional[Iterable[Text]] = None) -> None:
"""Command for generating the techlib of a core
:param args: Command arguments
"""
arg_parser = argparse.ArgumentParser(
description="Generate the verilog techlib of a core"
)
arg_parser.add_argument(
"core", help="The input core file",
)
arg_parser.add_argument(
"techlib", help="The output techlib file",
)
args = arg_parser.parse_args(args)
core_path = Path(args.core)
with core_path.open() as f:
core = load_core(f)
techlib_path = Path(args.techlib)
generate_techlib_cells(core, techlib_path)
def command_synthesize(args: Optional[Iterable[Text]] = None) -> None:
"""Command for synthesizing a design
@ -156,23 +181,23 @@ def command_synthesize(args: Optional[Iterable[Text]] = None) -> None:
with tempfile.TemporaryDirectory() as temp_dir:
work_dir = Path(temp_dir).resolve()
cells_map = work_dir / "cells_map.v"
generate_cells_map(core, cells_map)
cells_path = work_dir / "cells.v"
generate_techlib_cells(core, cells_path)
cells_sim = work_dir / "cells_sim.v"
generate_cells_sim(core, cells_sim)
cells_map_path = work_dir / "cells_map.v"
generate_cells_map(core, cells_map_path)
synth_script = work_dir / "synthesis.ys"
rtl_files = [
Path(input_file).resolve() for input_file in args.input_files
]
generate_synthesis_script(
core,
rtl_files,
cells_map,
cells_sim,
synth_script,
output_file=output_file,
core=core,
rtl_files=rtl_files,
cells_path=cells_path,
cells_map_path=cells_map_path,
path=synth_script,
netlist=output_file,
top=args.top,
flatten=args.flatten,
)


+ 33
- 8
src/kfpga/synthesis.py View File

@ -33,33 +33,58 @@
from pathlib import Path
import tempfile
from typing import Iterator, Optional, Text
from kfpga.hdl import get_hdl_template
from kfpga.models import Core
from kfpga.utils import get_template
def generate_cells_map(core: Core, path: Path) -> None:
"""generate the cells_map.v file
:param core: The core
:param path: The output file path
"""
path.parent.mkdir(mode=0o755, parents=True, exist_ok=True)
with path.open("w") as f:
template = get_hdl_template("synthesis/cells_map.v")
f.write(
template.render(
lut_size=core.lut_size, config_size=2 ** core.lut_size
)
)
def generate_synthesis_script(
core: Core,
rtl_files: Iterator[Path],
cells_map: Path,
cells_sim: Path,
cells_path: Path,
cells_map_path: Path,
path: Path,
output_file: Optional[Path] = None,
netlist: Optional[Path] = None,
top: Optional[Text] = None,
flatten: bool = False,
):
"""Generate the yosys synthesis script
:param path: The pbth of the output file
:param core: The targeted core
:param rtl_files: The RTL files to synthesize
:param cells_path: The cells techlib file
:param cells_map_path: The cells mapping file
:param path: The path to the generated yosys script
:param netlist: The path to the output netlist
:param top: The top module of the design
:param flatten: Should flatten the design?
"""
template = get_template("synthesis/synthesis.ys")
path.parent.mkdir(mode=0o755, parents=True, exist_ok=True)
with path.open("w") as f:
template = get_template("synthesis/synthesis.ys")
f.write(
template.render(
cells_map=cells_map,
cells_sim=cells_sim,
cells=cells_path,
cells_map=cells_map_path,
flatten=flatten,
lut_size=core.lut_size,
output_file=output_file,
output_file=netlist,
rtl_files=rtl_files,
top=top,
)


+ 4
- 20
src/kfpga/techlib.py View File

@ -35,31 +35,15 @@ from kfpga.hdl import get_hdl_template
from kfpga.models import Core
def generate_cells_map(core: Core, path: Path) -> None:
"""generate the cells_map.v file
def generate_techlib_cells(core: Core, path: Path) -> None:
"""generate the verilog cells file
:param core: The core
:param path: The output file path
"""
template = get_hdl_template("techlib/cells_map.v")
with path.open("w") as f:
f.write(
template.render(
lut_size=core.lut_size, config_size=2 ** core.lut_size
)
)
def generate_cells_sim(core: Core, path: Path) -> None:
"""generate the cells_sim.v file
:param core: The core
:param path: The output file path
"""
template = get_hdl_template("techlib/cells_sim.v")
path.parent.mkdir(mode=0o755, parents=True, exist_ok=True)
with path.open("w") as f:
template = get_hdl_template("techlib/cells.v")
f.write(
template.render(
lut_size=core.lut_size, config_size=2 ** core.lut_size


src/kfpga/templates/techlib/cells_map.v → src/kfpga/templates/synthesis/cells_map.v View File


+ 1
- 1
src/kfpga/templates/synthesis/synthesis.ys View File

@ -3,7 +3,7 @@
read_verilog {{ rtl_file }}
{% endfor %}
# Read the cells library
read_verilog -lib {{ cells_sim }}
read_verilog -lib {{ cells }}
# Elaborate the design
hierarchy -check {% if top %}-top {{ top }}{% else %}-auto-top{% endif %}


src/kfpga/templates/techlib/cells_sim.v → src/kfpga/templates/techlib/cells.v View File


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