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reorganize commands

master
parent
commit
e99bba4d3c
5 changed files with 67 additions and 39 deletions
  1. +1
    -3
      setup.cfg
  2. +3
    -36
      src/kfpga/commands.py
  3. +0
    -0
      src/kfpga/techlib/__init__.py
  4. +62
    -0
      src/kfpga/techlib/commands.py
  5. +1
    -0
      src/kfpga/testframework/__init__.py

+ 1
- 3
setup.cfg View File

@ -26,10 +26,8 @@ package_dir =
console_scripts =
kfpga-create-core = kfpga.commands:command_create_core
kfpga-generate-rtl = kfpga.commands:command_generate_rtl
kfpga-generate-techlib = kfpga.commands:command_generate_techlib
kfpga-synthesize = kfpga.synthesis.commands:command_synthesize
kfpga-generate-techlib = kfpga.techlib.commands:command_generate_techlib
kfpga-testframework-create-testsuite = kfpga.testframework.commands:command_create_testsuite
kfpga-testframework-generate-report = kfpga.testframework.commands:command_generate_report


+ 3
- 36
src/kfpga/commands.py View File

@ -32,18 +32,10 @@
# knowledge of the CeCILL-B license and that you accept its terms
import argparse
from pathlib import Path
import subprocess
import tempfile
from typing import Iterable, Optional, Text
from kfpga.api import (
Core,
generate_cells_map,
generate_techlib_cells,
generate_core_rtl,
generate_synthesis_script,
load_core,
save_core,
)
from kfpga.hdl_core import generate_core_rtl
from kfpga.io import load_core, save_core
from kfpga.models import Core
def command_create_core(args: Optional[Iterable[Text]] = None) -> None:
@ -119,28 +111,3 @@ def command_generate_rtl(args: Optional[Iterable[Text]] = None) -> None:
rtl_path = Path(args.rtl)
generate_core_rtl(core, rtl_path)
def command_generate_techlib(args: Optional[Iterable[Text]] = None) -> None:
"""Command for generating the techlib of a core
:param args: Command arguments
"""
arg_parser = argparse.ArgumentParser(
description="Generate the verilog techlib of a core"
)
arg_parser.add_argument(
"core", help="The input core file",
)
arg_parser.add_argument(
"techlib", help="The output techlib file",
)
args = arg_parser.parse_args(args)
core_path = Path(args.core)
with core_path.open() as f:
core = load_core(f)
techlib_path = Path(args.techlib)
generate_techlib_cells(core, techlib_path)

src/kfpga/techlib.py → src/kfpga/techlib/__init__.py View File


+ 62
- 0
src/kfpga/techlib/commands.py View File

@ -0,0 +1,62 @@
# Copyright Jonathan Tremesaygues (2019 - 2020)
#
# Jonathan Tremesaygues <jonathan.tremesaygues@slaanesh.org>
#
# This software is a computer program whose purpose is to [describe
# functionalities and technical features of your software].
#
# This software is governed by the CeCILL-B license under French law and
# abiding by the rules of distribution of free software. You can use,
# modify and/ or redistribute the software under the terms of the CeCILL-B
# license as circulated by CEA, CNRS and INRIA at the following URL
# "http://www.cecill.info".
#
# As a counterpart to the access to the source code and rights to copy,
# modify and redistribute granted by the license, users are provided only
# with a limited warranty and the software's author, the holder of the
# economic rights, and the successive licensors have only limited
# liability.
#
# In this respect, the user's attention is drawn to the risks associated
# with loading, using, modifying and/or developing or reproducing the
# software by the user in light of its specific status of free software,
# that may mean that it is complicated to manipulate, and that also
# therefore means that it is reserved for developers and experienced
# professionals having in-depth computer knowledge. Users are therefore
# encouraged to load and test the software's suitability as regards their
# requirements in conditions enabling the security of their systems and/or
# data to be ensured and, more generally, to use and operate it in the
# same conditions as regards security.
#
# The fact that you are presently reading this means that you have had
# knowledge of the CeCILL-B license and that you accept its terms
import argparse
from pathlib import Path
from typing import Iterable, Optional, Text
from kfpga.io import load_core
from kfpga.techlib import generate_techlib_cells
def command_generate_techlib(args: Optional[Iterable[Text]] = None) -> None:
"""Command for generating the techlib of a core
:param args: Command arguments
"""
arg_parser = argparse.ArgumentParser(
description="Generate the verilog techlib of a core"
)
arg_parser.add_argument(
"core", help="The input core file",
)
arg_parser.add_argument(
"techlib", help="The output techlib file",
)
args = arg_parser.parse_args(args)
core_path = Path(args.core)
with core_path.open() as f:
core = load_core(f)
techlib_path = Path(args.techlib)
generate_techlib_cells(core, techlib_path)

+ 1
- 0
src/kfpga/testframework/__init__.py View File

@ -40,6 +40,7 @@ from typing import Iterable
import xml.dom.minidom
from kfpga.utils import get_template
def generate_test_impl(output_dir: Path, app: Path, core: Path):
"""Generate a test


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