105 Commits (master)
 

Author SHA1 Message Date
  Jonathan Tremesaygues e99bba4d3c reorganize commands 1 year ago
  Jonathan Tremesaygues 46b66c5654 reorganize synthesis 1 year ago
  Jonathan Tremesaygues af90c46581 import testframework 1 year ago
  Jonathan Tremesaygues e609e15bde dffsr2dff removed from yosys? 1 year ago
  Jonathan Tremesaygues eabb0be96d fix install field 1 year ago
  Jonathan Tremesaygues 23a3f25a06 Use gitignore from https://github.com/github/gitignore/blob/master/Python.gitignore 1 year ago
  Jonathan Tremesaygues 63b5e7622d use a setup.cfg file for configuring the project 1 year ago
  Jonathan Tremesaygues b78b07093f add a command for generating the cells techlib, 1 year ago
  Jonathan Tremesaygues b09162532a Merge branch 'synthesis' 1 year ago
  Jonathan Tremesaygues e39d3c7c83 Update readme 1 year ago
  Jonathan Tremesaygues 2ea568f3ac Add command description 1 year ago
  Jonathan Tremesaygues 83dd462123 do the synthesize on a temp directory 1 year ago
  Jonathan Tremesaygues 2642dd448a oups, remove debug print 1 year ago
  Jonathan Tremesaygues 87f2065bb0 oups, add missing file 1 year ago
  Jonathan Tremesaygues 006fd47fbb Add a command for generating the RTL 1 year ago
  Jonathan Tremesaygues fb6b4f8926 add a command for generating the core file (yup, again) 1 year ago
  Jonathan Tremesaygues 8eb250fa93 fix type annotation 1 year ago
  Jonathan Tremesaygues 5146d75f9c fix type annotation 1 year ago
  Jonathan Tremesaygues aa3c62b3f9 begin work on synthesis 1 year ago
  Jonathan Tremesaygues 3e01c4609e Add missing typeng 1 year ago
  Jonathan Tremesaygues 79270156e6 Update copyright 1 year ago
  Jonathan Tremesaygues 497822bbf3 Add lut size in the cell name, differentiate DFF and DFFR 1 year ago
  Jonathan Tremesaygues d68635a544 Begin work on cell_map.v 1 year ago
  Jonathan Tremesaygues 9f3c75bdc6 Fix LUT input width 1 year ago
  Jonathan Tremesaygues 56cecb8338 use the port_index filter 1 year ago
  Jonathan Tremesaygues fb28c7a64a add a function for getting "hdl" templates 1 year ago
  Jonathan Tremesaygues 5310cfc9e3 Add missing files 1 year ago
  Jonathan Tremesaygues 8ce02fe015 New LUT implementation (mux cascading instead of a fat mux) 1 year ago
  Jonathan Tremesaygues 06a275a764 begin work on techlib 1 year ago
  Jonathan Tremesaygues 79c1429fc7 move jinja out 1 year ago
  Jonathan Tremesaygues a8eb5d4599 Use pathlib 1 year ago
  Jonathan Tremesaygues 8331cf1b7d reorganize HDL templates 1 year ago
  Jonathan Tremesaygues d4b89549f0 regroup useful stuff on an "API" module 1 year ago
  Jonathan Tremesaygues 34ee140e77 blackify 1 year ago
  Jonathan Tremesaygues 3dd930593f Add fake test for making jenkins happy 1 year ago
  Jonathan Tremesaygues 9a32646258 Update readme for API usage 1 year ago
  Jonathan Tremesaygues 9eebe675d8 Reorganize sources 1 year ago
  Jonathan Tremesaygues ae4017c73a fix LE template 1 year ago
  Jonathan Tremesaygues dd6b346640 clean up 1 year ago
  Jonathan Tremesaygues ceeb568d11 remove reference to set and enable signals, use single clock and reset 1 year ago
  Jonathan Tremesaygues 45889989a5 remove reference to set and enable signals, use single clock and reset 1 year ago
  Jonathan Tremesaygues d6bebd80d1 remove reference to set and enable signals 1 year ago
  Jonathan Tremesaygues 9e93965c12 Better verilog for Multiplexer 1 year ago
  Jonathan Tremesaygues 1b532f023a better verilog for ConfigurationStorage 1 year ago
  Jonathan Tremesaygues e2eda864e1 Update project URL 1 year ago
  Jonathan Tremesaygues 4136cb0e54 Update readme 1 year ago
  killruana bb96e90662 Use the good header 2 years ago
  killruana a634588edd oups 2 years ago
  killruana ece57160fd Update readme 2 years ago
  killruana 4e81b77ad8 remove useless spaces 2 years ago