A minimalist kFPGA core
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README.md

k1g1 - 1st generation kFPGA core with 1 logic element

This is the smallest FPGA core based on the first generation of the kFPGA architecture. It has the following characteristics :

  • a total of 4 I/O pairs
  • a grid of 1x1 logic tile
  • 1 logic element per tile
  • a 2-inputs LUT per logic element
  • 1 external clock, set, reset and enable signals

Yup, this is more a toy FPGA for validating the architecture rather than a real thing.

implementations

Qflow - OSU 0.35um

The core was succesfully implmented using the qflow toolchain and the OSU 0.35um standard cells. The implemented core has the following characteristics:

  • Netlist composed of 139 standard cells
  • Dimension of 208.0x130.0um, surface of 27040.0um² (0.02704mm²)
  • Maximal frequency of 200MHz

The core

You can run your own implementation with the following commands:

cd impl/qflow-osu035
qflow gui

Then click on the run buttons. QFlow GUI

Note: you must have qflow installed.