A minimalist kFPGA core
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test_dut.py 1.8KB

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  1. import itertools
  2. import cocotb
  3. from cocotb.clock import Clock
  4. from cocotb.triggers import Timer
  5. @cocotb.test()
  6. def test_or2(dut):
  7. """Test a sequential or2"""
  8. bitstream_width = 19
  9. bitstream = (
  10. ( # Switchbox
  11. (
  12. 0b011 # from south
  13. ) << 11
  14. | ( # To logic 0
  15. 0b100 # from west
  16. ) << 8
  17. | ( # To west
  18. 0b11 # from logic
  19. ) << 6
  20. | ( # To south
  21. 0b11 # from logic
  22. ) << 4
  23. | ( # To east
  24. 0b11 # from logic
  25. ) << 2
  26. | ( # To north
  27. 0b11 # from logic
  28. )
  29. ) << 5
  30. |
  31. ( # Logic element
  32. 0b1 << 4 # Enable LE DFF
  33. | 0b1110 # B | A
  34. )
  35. )
  36. cocotb.fork(Clock(dut.i_clks, 10, units='ns').start())
  37. cocotb.fork(Clock(dut.i_config_clk, 10, units='ns').start())
  38. # Sane values for inputs
  39. dut.i_sets = 0
  40. dut.i_nresets = 1
  41. dut.i_data_north = 0
  42. dut.i_data_east = 0
  43. dut.i_data_south = 0
  44. dut.i_data_west = 0
  45. dut.i_config = 0
  46. dut.i_config_enable = 0
  47. yield Timer(9, 'ns')
  48. # Send configuration
  49. dut.i_config_enable = 1
  50. for i in range(bitstream_width - 1, -1, -1):
  51. bit = bitstream >> i & 1
  52. dut.i_config = bit
  53. yield Timer(10, 'ns')
  54. dut.i_config_enable = 0
  55. # Test the functionality
  56. dut.i_enables = 1
  57. for _ in range(10):
  58. for b, a in itertools.product((False, True), repeat=2):
  59. dut.i_data_west = a
  60. dut.i_data_south = b
  61. yield Timer(10, 'ns')
  62. assert dut.o_data_north == a | b
  63. assert dut.o_data_east == a | b
  64. assert dut.o_data_south == a | b
  65. assert dut.o_data_west == a | b